diff --git a/pcbnew/drc/drc_engine.cpp b/pcbnew/drc/drc_engine.cpp index 97012f323d..45ecf3ff40 100644 --- a/pcbnew/drc/drc_engine.cpp +++ b/pcbnew/drc/drc_engine.cpp @@ -722,7 +722,12 @@ DRC_CONSTRAINT DRC_ENGINE::EvalRules( DRC_CONSTRAINT_T aConstraintType, const BO [&]( const DRC_ENGINE_CONSTRAINT* c ) { if( c->constraint.m_Value.HasMin() ) + { + if( c->parentRule && c->parentRule->m_Implicit ) + constraint.m_ImplicitMin = true; + constraint.m_Value.SetMin( c->constraint.m_Value.Min() ); + } if( c->constraint.m_Value.HasOpt() ) constraint.m_Value.SetOpt( c->constraint.m_Value.Opt() ); diff --git a/pcbnew/drc/drc_rule.h b/pcbnew/drc/drc_rule.h index cfca338d5a..4135b16ab5 100644 --- a/pcbnew/drc/drc_rule.h +++ b/pcbnew/drc/drc_rule.h @@ -125,7 +125,7 @@ public: class DRC_CONSTRAINT { - public: +public: DRC_CONSTRAINT( DRC_CONSTRAINT_T aType = NULL_CONSTRAINT, const wxString& aName = wxEmptyString ) : m_Type( aType ), @@ -133,6 +133,7 @@ class DRC_CONSTRAINT m_DisallowFlags( 0 ), m_ZoneConnection( ZONE_CONNECTION::INHERITED ), m_Test( nullptr ), + m_ImplicitMin( false ), m_name( aName ), m_parentRule( nullptr ) { @@ -190,6 +191,7 @@ public: int m_DisallowFlags; ZONE_CONNECTION m_ZoneConnection; DRC_RULE_CONDITION* m_Test; + bool m_ImplicitMin; private: wxString m_name; // For just-in-time constraints diff --git a/pcbnew/drc/drc_test_provider_hole_size.cpp b/pcbnew/drc/drc_test_provider_hole_size.cpp index 7d5257d430..7d9eeecba3 100644 --- a/pcbnew/drc/drc_test_provider_hole_size.cpp +++ b/pcbnew/drc/drc_test_provider_hole_size.cpp @@ -229,7 +229,7 @@ void DRC_TEST_PROVIDER_HOLE_SIZE::checkViaHole( PCB_VIA* via, bool aExceedMicro, if( fail_min ) { - if( constraint.GetParentRule() && constraint.GetParentRule()->m_Implicit ) + if( constraint.m_ImplicitMin ) constraintName = _( "board setup constraints" ); msg = formatMsg( _( "(%s min hole %s; actual %s)" ), diff --git a/pcbnew/drc/drc_test_provider_track_segment_length.cpp b/pcbnew/drc/drc_test_provider_track_segment_length.cpp index 42bb1cf599..3b122cec61 100644 --- a/pcbnew/drc/drc_test_provider_track_segment_length.cpp +++ b/pcbnew/drc/drc_test_provider_track_segment_length.cpp @@ -132,7 +132,7 @@ bool DRC_TEST_PROVIDER_TRACK_SEGMENT_LENGTH::Run() if( fail_min ) { - if( constraint.GetParentRule() && constraint.GetParentRule()->m_Implicit ) + if( constraint.m_ImplicitMin ) constraintName = _( "board setup constraints" ); msg = formatMsg( _( "(%s min length %s; actual %s)" ), diff --git a/pcbnew/drc/drc_test_provider_track_width.cpp b/pcbnew/drc/drc_test_provider_track_width.cpp index f5932f8f11..40c91e4041 100644 --- a/pcbnew/drc/drc_test_provider_track_width.cpp +++ b/pcbnew/drc/drc_test_provider_track_width.cpp @@ -131,7 +131,7 @@ bool DRC_TEST_PROVIDER_TRACK_WIDTH::Run() if( fail_min ) { - if( constraint.GetParentRule() && constraint.GetParentRule()->m_Implicit ) + if( constraint.m_ImplicitMin ) constraintName = _( "board setup constraints" ); msg = formatMsg( _( "(%s min width %s; actual %s)" ), diff --git a/pcbnew/drc/drc_test_provider_via_diameter.cpp b/pcbnew/drc/drc_test_provider_via_diameter.cpp index 227e12b629..a4cb6233af 100644 --- a/pcbnew/drc/drc_test_provider_via_diameter.cpp +++ b/pcbnew/drc/drc_test_provider_via_diameter.cpp @@ -117,7 +117,7 @@ bool DRC_TEST_PROVIDER_VIA_DIAMETER::Run() if( fail_min ) { - if( constraint.GetParentRule() && constraint.GetParentRule()->m_Implicit ) + if( constraint.m_ImplicitMin ) constraintName = _( "board setup constraints" ); msg = formatMsg( _( "(%s min diameter %s; actual %s)" ),