diff --git a/gerbview/export_to_pcbnew.cpp b/gerbview/export_to_pcbnew.cpp
index 0eafb7833a..e53ea72f8c 100644
--- a/gerbview/export_to_pcbnew.cpp
+++ b/gerbview/export_to_pcbnew.cpp
@@ -180,7 +180,7 @@ static int SavePcbFormatAscii( WinEDA_GerberFrame* frame, FILE* File,
// A spot is found, and can be a via: change it to via, and delete other
// spots at same location
- newtrack->m_Shape = VIA_NORMALE;
+ newtrack->m_Shape = VIA_THROUGH;
newtrack->SetLayer( 0x0F ); // Layers are 0 to 15 (Cu/Cmp)
@@ -205,7 +205,7 @@ static int SavePcbFormatAscii( WinEDA_GerberFrame* frame, FILE* File,
// delete redundant vias
for( track = Pcb->m_Track; track != NULL; track = track->Next() )
{
- if( track->m_Shape != VIA_NORMALE )
+ if( track->m_Shape != VIA_THROUGH )
continue;
// Search and delete others vias
@@ -213,7 +213,7 @@ static int SavePcbFormatAscii( WinEDA_GerberFrame* frame, FILE* File,
for( ; alt_track != NULL; alt_track = next_track )
{
next_track = alt_track->Next();
- if( alt_track->m_Shape != VIA_NORMALE )
+ if( alt_track->m_Shape != VIA_THROUGH )
continue;
if( alt_track->m_Start != track->m_Start )
diff --git a/pcbnew/class_board_item.cpp b/pcbnew/class_board_item.cpp
index ad3fb20da5..8d12d906f2 100644
--- a/pcbnew/class_board_item.cpp
+++ b/pcbnew/class_board_item.cpp
@@ -170,9 +170,9 @@ wxString BOARD_ITEM::MenuText( const BOARD* aPcb ) const
text << _( "Via" ) << wxT( " " ) << via->ShowWidth();
int shape = via->Shape();
- if( shape == BURIED_VIA )
+ if( shape == VIA_BURIED )
text << wxT(" ") << _( "Blind" );
- else if( shape == BLIND_VIA )
+ else if( shape == VIA_BLIND )
text << wxT(" ") << _("Buried");
// else say nothing about normal vias
@@ -182,7 +182,7 @@ wxString BOARD_ITEM::MenuText( const BOARD* aPcb ) const
text << wxT( " [" ) << net->m_Netname << wxT( "]" );
}
- if( shape != THROUGH_VIA )
+ if( shape != VIA_THROUGH )
{
// say which layers, only two for now
int topLayer;
diff --git a/pcbnew/class_track.cpp b/pcbnew/class_track.cpp
index 3bc6b290ee..a017078a83 100644
--- a/pcbnew/class_track.cpp
+++ b/pcbnew/class_track.cpp
@@ -8,6 +8,7 @@
#include "common.h"
#include "pcbnew.h"
+
#ifdef CVPCB
#include "cvpcb.h"
#endif
@@ -264,10 +265,10 @@ int TRACK::ReturnMaskLayer()
{
int via_type = Shape();
- if( via_type == THROUGH_VIA )
+ if( via_type == VIA_THROUGH )
return ALL_CU_LAYERS;
- // BLIND_VIA ou BURIED_VIA:
+ // VIA_BLIND ou VIA_BURIED:
int bottom_layer, top_layer;
@@ -302,7 +303,7 @@ void SEGVIA::SetLayerPair( int top_layer, int bottom_layer )
{
int via_type = Shape();
- if( via_type == THROUGH_VIA )
+ if( via_type == VIA_THROUGH )
{
top_layer = LAYER_CMP_N;
bottom_layer = COPPER_LAYER_N;
@@ -903,15 +904,15 @@ void SEGVIA::Show( int nestLevel, std::ostream& os )
switch( Shape() )
{
- case THROUGH_VIA:
+ case VIA_THROUGH:
cp = "through";
break;
- case BURIED_VIA:
+ case VIA_BURIED:
cp = "blind";
break;
- case BLIND_VIA:
+ case VIA_BLIND:
cp = "buried";
break;
diff --git a/pcbnew/class_track.h b/pcbnew/class_track.h
index 270b405ac5..dff4443265 100644
--- a/pcbnew/class_track.h
+++ b/pcbnew/class_track.h
@@ -9,11 +9,11 @@
// Via attributes (m_Shape parmeter)
-#define THROUGH_VIA 3 /* Always a through hole via */
-#define BURIED_VIA 2 /* this via can be on internal layers */
-#define BLIND_VIA 1 /* this via which connect from internal layers to an external layer */
-#define NOT_DEFINED_VIA 0 /* reserved (unused) */
-#define SQUARE_VIA_SHAPE 0x80000000 /* Flag pour forme carree */
+#define VIA_THROUGH 3 /* Always a through hole via */
+#define VIA_BURIED 2 /* this via can be on internal layers */
+#define VIA_BLIND 1 /* this via which connect from internal layers to an external layer */
+#define VIA_NOT_DEFINED 0 /* reserved (unused) */
+#define VIA_SQUARE_SHAPE 0x80000000 /* Flag pour forme carree */
/***/
diff --git a/pcbnew/classpcb.cpp b/pcbnew/classpcb.cpp
index 99383dcc1f..abd95905a4 100644
--- a/pcbnew/classpcb.cpp
+++ b/pcbnew/classpcb.cpp
@@ -433,7 +433,7 @@ EDA_BoardDesignSettings::EDA_BoardDesignSettings()
m_CopperLayerCount = 2; // Default design is a double sided board
m_ViaDrill = 250; // via drill (for the entire board)
m_CurrentViaSize = 450; // Current via size
- m_CurrentViaType = THROUGH_VIA; /* via type (BLIND, TROUGHT ...), bits 1 and 2 (not 0 and 1)*/
+ m_CurrentViaType = VIA_THROUGH; /* via type (BLIND, TROUGHT ...), bits 1 and 2 (not 0 and 1)*/
m_CurrentTrackWidth = 170; // current track width
for( ii = 0; ii < HIST0RY_NUMBER; ii++ )
{
@@ -454,9 +454,9 @@ EDA_BoardDesignSettings::EDA_BoardDesignSettings()
m_LayerColor[ii] = default_layer_color[ii];
// Layer colors (tracks and graphic items)
- m_ViaColor[BLIND_VIA] = CYAN;
- m_ViaColor[BURIED_VIA] = BROWN;
- m_ViaColor[THROUGH_VIA] = WHITE;
+ m_ViaColor[VIA_BLIND] = CYAN;
+ m_ViaColor[VIA_BURIED] = BROWN;
+ m_ViaColor[VIA_THROUGH] = WHITE;
m_ModuleTextCMPColor = LIGHTGRAY; // Text module color for modules on the COMPONENT layer
m_ModuleTextCUColor = MAGENTA; // Text module color for modules on the COPPER layer
m_ModuleTextNOVColor = DARKGRAY; // Text module color for "invisible" texts (must be BLACK if really not displayed)
diff --git a/pcbnew/clean.cpp b/pcbnew/clean.cpp
index dd3288c6f9..656518e968 100644
--- a/pcbnew/clean.cpp
+++ b/pcbnew/clean.cpp
@@ -81,7 +81,7 @@ void Clean_Pcb_Items( WinEDA_PcbFrame* frame, wxDC* DC )
TRACK* next_track;
for( track = frame->m_Pcb->m_Track; track != NULL; track = track->Next() )
{
- if( track->m_Shape != THROUGH_VIA )
+ if( track->m_Shape != VIA_THROUGH )
continue;
/* Search and delete others vias at same location */
@@ -89,7 +89,7 @@ void Clean_Pcb_Items( WinEDA_PcbFrame* frame, wxDC* DC )
for( ; alt_track != NULL; alt_track = next_track )
{
next_track = alt_track->Next();
- if( alt_track->m_Shape != THROUGH_VIA )
+ if( alt_track->m_Shape != VIA_THROUGH )
continue;
if( alt_track->m_Start != track->m_Start )
@@ -105,7 +105,7 @@ void Clean_Pcb_Items( WinEDA_PcbFrame* frame, wxDC* DC )
for( track = frame->m_Pcb->m_Track; track != NULL; track = next_track )
{
next_track = track->Next();
- if( track->m_Shape != THROUGH_VIA )
+ if( track->m_Shape != VIA_THROUGH )
continue;
D_PAD* pad = Fast_Locate_Pad_Connecte( frame->m_Pcb, track->m_Start, ALL_CU_LAYERS );
diff --git a/pcbnew/dialog_track_options.cpp b/pcbnew/dialog_track_options.cpp
index e26b19bdfa..a109e6f96e 100644
--- a/pcbnew/dialog_track_options.cpp
+++ b/pcbnew/dialog_track_options.cpp
@@ -251,11 +251,11 @@ void WinEDA_PcbTracksDialog::AcceptPcbOptions(wxCommandEvent& event)
/*******************************************************************/
{
g_DesignSettings.m_CurrentViaType = m_OptViaType->GetSelection() + 1;
- if ( g_DesignSettings.m_CurrentViaType != THROUGH_VIA )
+ if ( g_DesignSettings.m_CurrentViaType != VIA_THROUGH )
{
if( ! IsOK(this,
_("You have selected VIA Blind or VIA Buried\nWARNING: this feature is EXPERIMENTAL!!! Accept ?") ) )
- g_DesignSettings.m_CurrentViaType = THROUGH_VIA;
+ g_DesignSettings.m_CurrentViaType = VIA_THROUGH;
}
g_DesignSettings.m_CurrentViaSize =
diff --git a/pcbnew/editrack-part2.cpp b/pcbnew/editrack-part2.cpp
index 194845dfc3..74795dcaf4 100644
--- a/pcbnew/editrack-part2.cpp
+++ b/pcbnew/editrack-part2.cpp
@@ -231,12 +231,12 @@ void WinEDA_PcbFrame::Other_Layer_Route( TRACK* track, wxDC* DC )
GetScreen()->m_Active_Layer = GetScreen()->m_Route_Layer_BOTTOM;
/* Adjust the via layer pair */
- if( Via->Shape() == BURIED_VIA )
+ if( Via->Shape() == VIA_BURIED )
{
Via->SetLayerPair( old_layer, GetScreen()->m_Active_Layer );
}
- else if( Via->Shape() == BLIND_VIA ) //blind via
+ else if( Via->Shape() == VIA_BLIND ) //blind via
{
// A revoir! ( la via devrait deboucher sur 1 cote )
Via->SetLayerPair( old_layer, GetScreen()->m_Active_Layer );
diff --git a/pcbnew/pcbcfg.h b/pcbnew/pcbcfg.h
index 4a14c4adba..29589db995 100644
--- a/pcbnew/pcbcfg.h
+++ b/pcbnew/pcbcfg.h
@@ -140,7 +140,7 @@ static PARAM_CFG_INT TypeViaCfg
(
wxT( "TypeVia" ), /* Keyword */
& g_DesignSettings.m_CurrentViaType, /* Parameter address */
- VIA_NORMALE, /* Default value */
+ VIA_THROUGH, /* Default value */
0, 3 /* Valeurs extremes */
);
@@ -586,7 +586,7 @@ static PARAM_CFG_SETCOLOR ColorViaNormCfg
(
INSETUP,
wxT( "CoViaNo" ), /* Keyword */
- & g_DesignSettings.m_ViaColor[VIA_NORMALE], /* Parameter address */
+ & g_DesignSettings.m_ViaColor[VIA_THROUGH], /* Parameter address */
LIGHTGRAY /* Default value */
);
@@ -594,7 +594,7 @@ static PARAM_CFG_SETCOLOR ColorViaborgneCfg
(
INSETUP,
wxT( "CoViaBo" ), /* Keyword */
- & g_DesignSettings.m_ViaColor[VIA_BORGNE], /* Parameter address */
+ & g_DesignSettings.m_ViaColor[VIA_BURIED], /* Parameter address */
CYAN /* Default value */
);
@@ -602,7 +602,7 @@ static PARAM_CFG_SETCOLOR ColorViaEnterreeCfg // Buried Via Color
(
INSETUP,
wxT( "CoViaEn" ), /* Keyword */
- & g_DesignSettings.m_ViaColor[VIA_ENTERREE], /* Parameter address */
+ & g_DesignSettings.m_ViaColor[VIA_BLIND], /* Parameter address */
BROWN /* Default value */
);
diff --git a/pcbnew/router.cpp b/pcbnew/router.cpp
index 6063e3ec19..2e9cef6f77 100644
--- a/pcbnew/router.cpp
+++ b/pcbnew/router.cpp
@@ -604,9 +604,9 @@ void WinEDA_PcbFrame::ReadAutoroutedTracks( wxDC* DC )
NewVia->m_Width = via_size;
NewVia->SetLayer( via_layer1 + (via_layer2 << 4) );
if( NewVia->GetLayer() == 0x0F || NewVia->GetLayer() == 0xF0 )
- NewVia->m_Shape = THROUGH_VIA;
+ NewVia->m_Shape = VIA_THROUGH;
else
- NewVia->m_Shape = BURIED_VIA;
+ NewVia->m_Shape = VIA_BURIED;
NewVia->Insert( m_Pcb, NULL );
NbTrack++;
diff --git a/pcbnew/set_color.h b/pcbnew/set_color.h
index a21b7aaa74..e2c24e59f0 100644
--- a/pcbnew/set_color.h
+++ b/pcbnew/set_color.h
@@ -249,27 +249,27 @@ static ColorButton Msg_Others_Items =
wxT( "Others" ), -1 // Title
};
-static ColorButton Via_Normale_Butt =
+static ColorButton VIA_THROUGH_Butt =
{
wxT( "*" ),
- VIA_NORMALE, // Layer
- &g_DesignSettings.m_ViaColor[VIA_NORMALE], // Address of optional parameter
+ VIA_THROUGH, // Layer
+ &g_DesignSettings.m_ViaColor[VIA_THROUGH], // Address of optional parameter
TRUE // Toggle ITEM_NOT_SHOW bit of the color variable
};
static ColorButton Via_Aveugle_Butt =
{
wxT( "*" ),
- VIA_ENTERREE, // Layer
- &g_DesignSettings.m_ViaColor[VIA_ENTERREE], // Address of optional parameter
+ VIA_BLIND, // Layer
+ &g_DesignSettings.m_ViaColor[VIA_BLIND], // Address of optional parameter
TRUE // Toggle ITEM_NOT_SHOW bit of the color variable
};
static ColorButton Via_Borgne_Butt =
{
wxT( "*" ),
- VIA_BORGNE, // Layer
- &g_DesignSettings.m_ViaColor[VIA_BORGNE], // Address of optional parameter
+ VIA_BURIED, // Layer
+ &g_DesignSettings.m_ViaColor[VIA_BURIED], // Address of optional parameter
TRUE // Toggle ITEM_NOT_SHOW bit of the color variable
};
@@ -414,7 +414,7 @@ static ColorButton* laytool_list[] = {
// &Layer_32_Butt,
&Msg_Others_Items,
- &Via_Normale_Butt,
+ &VIA_THROUGH_Butt,
&Via_Aveugle_Butt,
&Via_Borgne_Butt,
&Ratsnest_Butt,
diff --git a/pcbnew/swap_layers.cpp b/pcbnew/swap_layers.cpp
index a2b5d662f1..404e4c8f42 100644
--- a/pcbnew/swap_layers.cpp
+++ b/pcbnew/swap_layers.cpp
@@ -218,7 +218,7 @@ void WinEDA_PcbFrame::Swap_Layers( wxCommandEvent& event )
if( pt_segm->Type() == TYPEVIA )
{
SEGVIA* Via = (SEGVIA*) pt_segm;
- if( Via->Shape() == THROUGH_VIA )
+ if( Via->Shape() == VIA_THROUGH )
continue;
int top_layer, bottom_layer;
Via->ReturnLayerPair( &top_layer, &bottom_layer );