Add regression test and example rule.

Fixes https://gitlab.com/kicad/code/kicad/-/issues/18142

pcbnew/dialogs/panel_setup_rules_help.md

@@ -298,12 +298,19 @@ For the latter use a `(layer "layer_name")` clause in the rule.
     (rule "Plated through-hole size"
         (constraint hole_size (min 0.2mm) (max 6.35mm))
         (condition "A.isPlated() && A.Hole_Size_X == A.Hole_Size_Y"))
-
     (rule "Plated slot size"
         (constraint hole_size (min 0.5mm))
         (condition "A.isPlated() && A.Hole_Size_X != A.Hole_Size_Y"))
 
 
+    # Allow blind/buried to micro-via hole-to-hole violations when it is known that
+    # the fab will mechanically drill blind/buried via holes -before- laser drilling 
+    # micro-vias.
+    (rule hole_to_hole_uvia_exclusion
+        (condition "A.Via_Type == 'Blind/buried' && B.Via_Type == 'Micro'")
+        (constraint hole_to_hole)
+        (severity ignore))
+
 ### Documentation
 
 For the full documentation see [https://docs.kicad.org](https://docs.kicad.org/GetMajorMinorVersion/en/pcbnew/pcbnew.html#custom_design_rules).

pcbnew/dialogs/panel_setup_rules_help_md.h

@@ -299,12 +299,19 @@ _HKI( "### Top-level Clauses\n"
 "    (rule \"Plated through-hole size\"\n"
 "        (constraint hole_size (min 0.2mm) (max 6.35mm))\n"
 "        (condition \"A.isPlated() && A.Hole_Size_X == A.Hole_Size_Y\"))\n"
-"\n"
 "    (rule \"Plated slot size\"\n"
 "        (constraint hole_size (min 0.5mm))\n"
 "        (condition \"A.isPlated() && A.Hole_Size_X != A.Hole_Size_Y\"))\n"
 "\n"
 "\n"
+"    # Allow blind/buried to micro-via hole-to-hole violations when it is known that\n"
+"    # the fab will mechanically drill blind/buried via holes -before- laser drilling \n"
+"    # micro-vias.\n"
+"    (rule hole_to_hole_uvia_exclusion\n"
+"        (condition \"A.Via_Type == 'Blind/buried' && B.Via_Type == 'Micro'\")\n"
+"        (constraint hole_to_hole)\n"
+"        (severity ignore))\n"
+"\n"
 "### Documentation\n"
 "\n"
 "For the full documentation see [https://docs.kicad.org](https://docs.kicad.org/GetMajorMinorVersion/en/pcbnew/pcbnew.html#custom_design_rules)." );

qa/tests/pcbnew/drc/test_drc_regressions.cpp

@@ -139,6 +139,7 @@ BOOST_FIXTURE_TEST_CASE( DRCFalseNegativeRegressions, DRC_REGRESSION_TEST_FIXTUR
         { "issue12109", 8 },        // Pads fail annular width test
         { "issue14334", 2 },        // Thermal spoke to otherwise unconnected island
         { "issue16566", 6 },        // Pad_Shape vs Shape property
+        { "issue18142", 1 },        // blind/buried via to micro-via hole-to-hole
         { "reverse_via", 3 },       // Via/track ordering
         { "intersectingzones", 1 }, // zones are too close to each other
         { "fill_bad",   1 },        // zone max BBox was too small