diff --git a/common/swig/dlist.i b/common/swig/dlist.i
index 72d6f360a3..fc39ce956d 100644
--- a/common/swig/dlist.i
+++ b/common/swig/dlist.i
@@ -39,7 +39,10 @@
def __init__(self,aList):
self.last = aList # last item is the start of list
- def next(self): # get the next item
+ def next(self): # get the next item, Python 2 way to implement an iterator
+ return self.__next__()
+
+ def __next__(self): # get the next item
item = self.last
try:
diff --git a/common/swig/kiway.i b/common/swig/kiway.i
index df8873385f..008bf3b065 100644
--- a/common/swig/kiway.i
+++ b/common/swig/kiway.i
@@ -220,28 +220,28 @@ if os.path.exists(libcef_so):
%{
def OnPgmInit(self):
- print "hereA"
+ print("hereA")
if not self.InitPgm():
return False;
- print "hereB"
+ print("hereB")
try:
# A KIWAY_PLAYER is a wx.Window
frame = Kiway.Player( FRAME_SCH, True )
- print "here0"
+ print("here0")
except IOError as e:
- print 'Player()', e
+ print('Player()', e)
return None
- print "here1"
+ print("here1")
Kiway.SetTop(frame)
- print "here2"
+ print("here2")
return frame
%}
diff --git a/pcbnew/python/examples/createPcb.py b/pcbnew/python/examples/createPcb.py
index 1f4a8546b0..67af965de4 100644
--- a/pcbnew/python/examples/createPcb.py
+++ b/pcbnew/python/examples/createPcb.py
@@ -1,4 +1,7 @@
-#!/usr/bin/env python2.7
+#!/usr/bin/env python
+
+from __future__ import print_function
+
from pcbnew import *
size_0_6mm = wxSizeMM(0.6,0.6)
@@ -38,11 +41,11 @@ pcb.Save("my2.kicad_pcb")
pcb = LoadBoard("my2.kicad_pcb")
-print map( lambda x: x.GetReference() , list(pcb.GetModules()))
+print(map( lambda x: x.GetReference() , list(pcb.GetModules())))
for m in pcb.GetModules():
for p in m.Pads():
- print 'pad ', p.GetName(), p.GetPosition(), p.GetOffset()
+ print('pad ', p.GetName(), p.GetPosition(), p.GetOffset())
# pcb.GetDesignSettings()
diff --git a/pcbnew/python/examples/hidePcbValuesShowReferences.py b/pcbnew/python/examples/hidePcbValuesShowReferences.py
index 44b0738a99..e90598764a 100644
--- a/pcbnew/python/examples/hidePcbValuesShowReferences.py
+++ b/pcbnew/python/examples/hidePcbValuesShowReferences.py
@@ -7,7 +7,7 @@ filename=sys.argv[1]
pcb = LoadBoard(filename)
for module in pcb.GetModules():
- print "* Module: %s"%module.GetReference()
+ print("* Module: %s" % module.GetReference())
module.Value().SetVisible(False) # set Value as Hidden
module.Reference().SetVisible(True) # set Reference as Visible
diff --git a/pcbnew/python/examples/listPcb.py b/pcbnew/python/examples/listPcb.py
index f36031f664..089dac172e 100644
--- a/pcbnew/python/examples/listPcb.py
+++ b/pcbnew/python/examples/listPcb.py
@@ -1,4 +1,7 @@
#!/usr/bin/env python
+
+from __future__ import print_function
+
import sys
from pcbnew import *
@@ -11,7 +14,7 @@ FromUnits = FromMM
#ToUnits=ToMils
#FromUnits=FromMils
-print "LISTING VIAS:"
+print("LISTING VIAS:")
for item in pcb.GetTracks():
if type(item) is VIA:
@@ -19,7 +22,7 @@ for item in pcb.GetTracks():
pos = item.GetPosition()
drill = item.GetDrillValue()
width = item.GetWidth()
- print " * Via: %s - %f/%f "%(ToUnits(pos),ToUnits(drill),ToUnits(width))
+ print(" * Via: %s - %f/%f " % (ToUnits(pos), ToUnits(drill), ToUnits(width)))
elif type(item) is TRACK:
@@ -27,40 +30,39 @@ for item in pcb.GetTracks():
end = item.GetEnd()
width = item.GetWidth()
- print " * Track: %s to %s, width %f" % (ToUnits(start),ToUnits(end),ToUnits(width))
+ print(" * Track: %s to %s, width %f" % (ToUnits(start), ToUnits(end), ToUnits(width)))
else:
- print "Unknown type %s" % type(item)
+ print("Unknown type %s" % type(item))
-print ""
-print "LIST DRAWINGS:"
+print("")
+print("LIST DRAWINGS:")
for item in pcb.GetDrawings():
if type(item) is TEXTE_PCB:
- print "* Text: '%s' at %s"%(item.GetText(), item.GetPosition())
+ print("* Text: '%s' at %s" % (item.GetText(), item.GetPosition()))
elif type(item) is DRAWSEGMENT:
- print "* Drawing: %s"%item.GetShapeStr() # dir(item)
+ print("* Drawing: %s" % item.GetShapeStr()) # dir(item)
else:
- print type(item)
+ print(type(item))
-print ""
-print "LIST MODULES:"
+print("")
+print("LIST MODULES:")
for module in pcb.GetModules():
- print "* Module: %s at %s"%(module.GetReference(), ToUnits(module.GetPosition()))
+ print("* Module: %s at %s" % (module.GetReference(), ToUnits(module.GetPosition())))
-print ""
-print "Nets cnt: ", pcb.GetNetCount()
-print "track w cnt:",len(pcb.GetTrackWidthList())
-print "via s cnt:",len(pcb.GetViasDimensionsList())
+print("")
+print("Nets cnt: ", pcb.GetNetCount())
+print("track w cnt:", len(pcb.GetTrackWidthList()))
+print("via s cnt:", len(pcb.GetViasDimensionsList()))
-print ""
-print "LIST ZONES:", pcb.GetAreaCount()
+print("")
+print("LIST ZONES:", pcb.GetAreaCount())
for idx in range(0, pcb.GetAreaCount()):
zone=pcb.GetArea(idx)
- print "zone:", idx, "priority:", zone.GetPriority(), "netname", zone.GetNetname()
-
-print ""
-print "NetClasses:", pcb.GetNetClasses().GetCount(),
+ print("zone:", idx, "priority:", zone.GetPriority(), "netname", zone.GetNetname())
+print("")
+print("NetClasses:", pcb.GetNetClasses().GetCount())
diff --git a/pcbnew/swig/tests/test1.py b/pcbnew/swig/tests/test1.py
index fbcb9deb31..03c18fa31f 100644
--- a/pcbnew/swig/tests/test1.py
+++ b/pcbnew/swig/tests/test1.py
@@ -1,11 +1,11 @@
+from __future__ import print_function
+
import pcbnew
pcb = pcbnew.GetBoard()
for m in pcb.GetModules():
- print m.GetPosition()
+ print(m.GetPosition())
for p in m.Pads():
- print "p=>",p.GetPosition(),p.GetName()
- print p.GetPosition()
-
-
+ print("p=>", p.GetPosition(), p.GetName())
+ print(p.GetPosition())
diff --git a/pcbnew/swig/tests/test2.py b/pcbnew/swig/tests/test2.py
index b27ea14a71..f2ca27c9dd 100644
--- a/pcbnew/swig/tests/test2.py
+++ b/pcbnew/swig/tests/test2.py
@@ -1,8 +1,10 @@
+from __future__ import print_function
+
import pcbnew
pcb = pcbnew.GetBoard()
for m in pcb.GetModules():
- print m.GetReference(),"(",m.GetValue(),") at ", m.GetPosition()
+ print(m.GetReference(), "(", m.GetValue(), ") at ", m.GetPosition())
for p in m.Pads():
- print " pad",p.GetName(), "at",p.GetPosition()
+ print(" pad", p.GetName(), "at", p.GetPosition())
diff --git a/qa/testcases/test_001_pcb_load.py b/qa/testcases/test_001_pcb_load.py
index 8e9aea9457..545b732ce3 100644
--- a/qa/testcases/test_001_pcb_load.py
+++ b/qa/testcases/test_001_pcb_load.py
@@ -7,42 +7,41 @@ class TestPCBLoad(unittest.TestCase):
def setUp(self):
self.pcb = pcbnew.LoadBoard("data/complex_hierarchy.kicad_pcb")
-
+
def test_pcb_load(self):
- self.assertNotEqual(self.pcb,None)
+ self.assertNotEqual(self.pcb,None)
def test_pcb_track_count(self):
- tracks = list(self.pcb.GetTracks())
- self.assertEqual(len(tracks),361)
+ tracks = list(self.pcb.GetTracks())
+ self.assertEqual(len(tracks),361)
def test_pcb_modules(self):
- modules = list(self.pcb.GetModules())
+ modules = list(self.pcb.GetModules())
self.assertEqual(len(modules), 72)
def test_pcb_module_references(self):
- board_refs = list(module.GetReference() for
- module in self.pcb.GetModules())
+ board_refs = list(module.GetReference() for
+ module in self.pcb.GetModules())
- known_refs = [u'P1', u'P3', u'C2', u'C1', u'D1', u'Q3', u'Q5', u'Q7',
- u'Q6', u'Q1', u'Q2', u'Q4', u'Q8', u'P2', u'U1', u'U4',
- u'P4', u'P5', u'P6', u'U3', u'R9', u'R15', u'RV1', u'RV2',
- u'C3', u'C4', u'C5', u'C6', u'C7', u'C8', u'C9', u'D2',
- u'D3', u'D4', u'D5', u'D6', u'D7', u'R3', u'R4', u'R5',
- u'R6', u'R7', u'R8', u'R10', u'R11', u'R12', u'R13',
- u'R14', u'R16', u'R17', u'R18', u'R19', u'R20', u'R21',
- u'R22', u'MIRE', u'C10', u'C11',
- u'U2', u'C14', u'C12', u'R23', u'R24', u'D9', u'D8', u'R25',
- u'R26', u'R27', u'R28']
+ known_refs = [u'P1', u'P3', u'C2', u'C1', u'D1', u'Q3', u'Q5', u'Q7',
+ u'Q6', u'Q1', u'Q2', u'Q4', u'Q8', u'P2', u'U1', u'U4',
+ u'P4', u'P5', u'P6', u'U3', u'R9', u'R15', u'RV1', u'RV2',
+ u'C3', u'C4', u'C5', u'C6', u'C7', u'C8', u'C9', u'D2',
+ u'D3', u'D4', u'D5', u'D6', u'D7', u'R3', u'R4', u'R5',
+ u'R6', u'R7', u'R8', u'R10', u'R11', u'R12', u'R13',
+ u'R14', u'R16', u'R17', u'R18', u'R19', u'R20', u'R21',
+ u'R22', u'MIRE', u'C10', u'C11',
+ u'U2', u'C14', u'C12', u'R23', u'R24', u'D9', u'D8', u'R25',
+ u'R26', u'R27', u'R28']
+
+ for ref in known_refs:
+ self.assertTrue(ref in board_refs)
- for ref in known_refs:
- self.assertTrue(ref in board_refs)
-
def test_pcb_netcount(self):
- self.assertEqual(self.pcb.GetNetCount(),51)
+ self.assertEqual(self.pcb.GetNetCount(),51)
#def test_interactive(self):
- # code.interact(local=locals())
+ # code.interact(local=locals())
if __name__ == '__main__':
unittest.main()
-
\ No newline at end of file