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Power Symbols: automatically fix mismatched legacy symbols, add tests

Browse Source 
Has netlist generation test for legacy power symbols, and test for
fixing legacy mismatched power symbol text fields and invisible pin names.
This commit is contained in:
Mike Williams 2023-02-20 12:55:02 -05:00
parent 5995e0e516
commit 959a19a461
23 changed files with 1271 additions and 3 deletions

6
eeschema/eeschema.cpp
View File

@ -93,6 +93,10 @@ static std::unique_ptr<SCHEMATIC> readSchematicFromFile( const std::string& aFil
// Restore all of the loaded symbol instances from the root sheet screen.
sheets.UpdateSymbolInstanceData( schematic->RootScreen()->GetSymbolInstances() );
if( schematic->RootScreen()->GetFileFormatVersionAtLoad() < 20230221 )
for( SCH_SCREEN* screen = screens.GetFirst(); screen; screen = screens.GetNext() )
screen->FixLegacyPowerSymbolMismatches();
for( SCH_SCREEN* screen = screens.GetFirst(); screen; screen = screens.GetNext() )
screen->MigrateSimModels();
@ -581,4 +585,4 @@ void IFACE::SaveFileAs( const wxString& aProjectBasePath, const wxString& aProje
int IFACE::HandleJob( JOB* aJob )
{
return m_jobHandler->RunJob( aJob );
}
}

5
eeschema/eeschema_helpers.cpp
View File

@ -146,6 +146,9 @@ SCHEMATIC* EESCHEMA_HELPERS::LoadSchematic( wxString& aFileName, SCH_IO_MGR::SCH
sheetList.UpdateSheetInstanceData( schematic->RootScreen()->GetSheetInstances());
if( schematic->RootScreen()->GetFileFormatVersionAtLoad() < 20230221 )
screens.FixLegacyPowerSymbolMismatches();
for( SCH_SCREEN* screen = screens.GetFirst(); screen; screen = screens.GetNext() )
screen->MigrateSimModels();
@ -172,4 +175,4 @@ SCHEMATIC* EESCHEMA_HELPERS::LoadSchematic( wxString& aFileName, SCH_IO_MGR::SCH
return schematic;
}
}

7
eeschema/files-io.cpp
View File

@ -432,6 +432,9 @@ bool SCH_EDIT_FRAME::OpenProjectFiles( const std::vector<wxString>& aFileSet, in
// to the s-expression format.
schematic.ReplaceDuplicateTimeStamps();
for( SCH_SCREEN* screen = schematic.GetFirst(); screen; screen = schematic.GetNext() )
screen->FixLegacyPowerSymbolMismatches();
// Allow the schematic to be saved to new file format without making any edits.
OnModify();
}
@ -456,6 +459,10 @@ bool SCH_EDIT_FRAME::OpenProjectFiles( const std::vector<wxString>& aFileSet, in
if( Schematic().RootScreen()->GetFileFormatVersionAtLoad() < 20221110 )
sheetList.UpdateSheetInstanceData( Schematic().RootScreen()->GetSheetInstances());
if( Schematic().RootScreen()->GetFileFormatVersionAtLoad() < 20230221 )
for( SCH_SCREEN* screen = schematic.GetFirst(); screen; screen = schematic.GetNext() )
screen->FixLegacyPowerSymbolMismatches();
for( SCH_SCREEN* screen = schematic.GetFirst(); screen; screen = schematic.GetNext() )
screen->MigrateSimModels();
}

3
eeschema/sch_file_versions.h
View File

@ -94,4 +94,5 @@
//#define SEXPR_SCHEMATIC_FILE_VERSION 20221110 // Move sheet instance data to sheet definition.
//#define SEXPR_SCHEMATIC_FILE_VERSION 20221126 // Remove value and footprint from instance data.
//#define SEXPR_SCHEMATIC_FILE_VERSION 20221206 // Simulation model fields V6 -> V7
#define SEXPR_SCHEMATIC_FILE_VERSION 20230121 // SCH_MARKER specific sheet path serialisation
//#define SEXPR_SCHEMATIC_FILE_VERSION 20230121 // SCH_MARKER specific sheet path serialisation
#define SEXPR_SCHEMATIC_FILE_VERSION 20230221 // Modern power symbols (editable value = net)

27
eeschema/sch_screen.cpp
View File

@ -1576,6 +1576,26 @@ void SCH_SCREEN::SetLegacySymbolInstanceData()
}
void SCH_SCREEN::FixLegacyPowerSymbolMismatches()
{
for( SCH_ITEM* item : Items().OfType( SCH_SYMBOL_T ) )
{
SCH_SYMBOL* symbol = static_cast<SCH_SYMBOL*>( item );
// Fix pre-8.0 legacy power symbols with invisible pins
// that have mismatched pin names and value fields
if( symbol->GetLibSymbolRef()
&& symbol->GetLibSymbolRef()->IsPower()
&& symbol->GetAllLibPins().size() > 0
&& symbol->GetAllLibPins()[0]->IsGlobalPower()
&& !symbol->GetAllLibPins()[0]->IsVisible() )
{
symbol->SetValueFieldText( symbol->GetAllLibPins()[0]->GetName() );
}
}
}
size_t SCH_SCREEN::getLibSymbolNameMatches( const SCH_SYMBOL& aSymbol,
std::vector<wxString>& aMatches )
{
@ -2002,6 +2022,13 @@ void SCH_SCREENS::SetLegacySymbolInstanceData()
}
void SCH_SCREENS::FixLegacyPowerSymbolMismatches()
{
for( SCH_SCREEN* screen = GetFirst(); screen; screen = GetNext() )
screen->FixLegacyPowerSymbolMismatches();
}
void SCH_SCREEN::MigrateSimModels()
{
LOCALE_IO toggle;

12
eeschema/sch_screen.h
View File

@ -532,6 +532,12 @@ public:
*/
void SetLegacySymbolInstanceData();
/**
* Fix legacy power symbols that have mismatched value text fields
* and invisible power pin names.
*/
void FixLegacyPowerSymbolMismatches();
/**
* Check all symbol default instance to see if they are not set yet.
*/
@ -782,6 +788,12 @@ public:
*/
void SetLegacySymbolInstanceData();
/**
* Fix legacy power symbols that have mismatched value text fields
* and invisible power pin names.
*/
void FixLegacyPowerSymbolMismatches();
private:
void addScreenToList( SCH_SCREEN* aScreen, SCH_SHEET* aSheet );
void buildScreenList( SCH_SHEET* aSheet);

qa/data/eeschema/netlists/legacy_power/legacy_power.kicad_pcb
Normal file
View File

LOADING design file

326
qa/data/eeschema/netlists/legacy_power/legacy_power.kicad_pro Normal file
View File

@ -0,0 +1,326 @@
{
"board": {
"design_settings": {
"defaults": {
"board_outline_line_width": 0.1,
"copper_line_width": 0.2,
"copper_text_size_h": 1.5,
"copper_text_size_v": 1.5,
"copper_text_thickness": 0.3,
"other_line_width": 0.15,
"silk_line_width": 0.15,
"silk_text_size_h": 1.0,
"silk_text_size_v": 1.0,
"silk_text_thickness": 0.15
},
"diff_pair_dimensions": [],
"drc_exclusions": [],
"rules": {
"min_copper_edge_clearance": 0.0,
"solder_mask_clearance": 0.0,
"solder_mask_min_width": 0.0
},
"track_widths": [],
"via_dimensions": []
},
"layer_presets": []
},
"boards": [],
"cvpcb": {
"equivalence_files": []
},
"erc": {
"erc_exclusions": [],
"meta": {
"version": 0
},
"pin_map": [
[
0,
0,
0,
0,
0,
0,
1,
0,
0,
0,
0,
2
],
[
0,
2,
0,
1,
0,
0,
1,
0,
2,
2,
2,
2
],
[
0,
0,
0,
0,
0,
0,
1,
0,
1,
0,
1,
2
],
[
0,
1,
0,
0,
0,
0,
1,
1,
2,
1,
1,
2
],
[
0,
0,
0,
0,
0,
0,
1,
0,
0,
0,
0,
2
],
[
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
2
],
[
1,
1,
1,
1,
1,
0,
1,
1,
1,
1,
1,
2
],
[
0,
0,
0,
1,
0,
0,
1,
0,
0,
0,
0,
2
],
[
0,
2,
1,
2,
0,
0,
1,
0,
2,
2,
2,
2
],
[
0,
2,
0,
1,
0,
0,
1,
0,
2,
0,
0,
2
],
[
0,
2,
1,
1,
0,
0,
1,
0,
2,
0,
0,
2
],
[
2,
2,
2,
2,
2,
2,
2,
2,
2,
2,
2,
2
]
],
"rule_severities": {
"bus_definition_conflict": "error",
"bus_entry_needed": "error",
"bus_label_syntax": "error",
"bus_to_bus_conflict": "error",
"bus_to_net_conflict": "error",
"different_unit_footprint": "error",
"different_unit_net": "error",
"duplicate_reference": "error",
"duplicate_sheet_names": "error",
"extra_units": "error",
"global_label_dangling": "warning",
"hier_label_mismatch": "error",
"label_dangling": "error",
"lib_symbol_issues": "warning",
"multiple_net_names": "warning",
"net_not_bus_member": "warning",
"no_connect_connected": "warning",
"no_connect_dangling": "warning",
"pin_not_connected": "error",
"pin_not_driven": "error",
"pin_to_pin": "warning",
"power_pin_not_driven": "error",
"similar_labels": "warning",
"unannotated": "error",
"unit_value_mismatch": "error",
"unresolved_variable": "error",
"wire_dangling": "error"
}
},
"libraries": {
"pinned_footprint_libs": [],
"pinned_symbol_libs": []
},
"meta": {
"filename": "legacy_power.kicad_pro",
"version": 1
},
"net_settings": {
"classes": [
{
"bus_width": 12.0,
"clearance": 0.2,
"diff_pair_gap": 0.25,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.2,
"line_style": 0,
"microvia_diameter": 0.3,
"microvia_drill": 0.1,
"name": "Default",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.25,
"via_diameter": 0.8,
"via_drill": 0.4,
"wire_width": 6.0
}
],
"meta": {
"version": 2
},
"net_colors": null
},
"pcbnew": {
"last_paths": {
"gencad": "",
"idf": "",
"netlist": "",
"specctra_dsn": "",
"step": "",
"vrml": ""
},
"page_layout_descr_file": ""
},
"schematic": {
"annotate_start_num": 0,
"drawing": {
"default_line_thickness": 6.0,
"default_text_size": 50.0,
"field_names": [],
"intersheets_ref_own_page": false,
"intersheets_ref_prefix": "",
"intersheets_ref_short": false,
"intersheets_ref_show": false,
"intersheets_ref_suffix": "",
"junction_size_choice": 3,
"label_size_ratio": 0.375,
"pin_symbol_size": 25.0,
"text_offset_ratio": 0.15
},
"legacy_lib_dir": "",
"legacy_lib_list": [],
"meta": {
"version": 1
},
"net_format_name": "KiCad",
"ngspice": {
"fix_include_paths": true,
"fix_passive_vals": false,
"meta": {
"version": 0
},
"model_mode": 0,
"workbook_filename": ""
},
"page_layout_descr_file": "",
"plot_directory": "",
"spice_adjust_passive_values": false,
"spice_external_command": "spice \"%I\"",
"subpart_first_id": 65,
"subpart_id_separator": 0
},
"sheets": [
[
"c57b0c1c-467a-41e5-ac2b-67db44aab898",
""
]
],
"text_variables": {}
}

qa/data/eeschema/netlists/legacy_power/legacy_power.kicad_sch
Normal file
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LOADING design file

85
qa/data/eeschema/netlists/legacy_power/legacy_power.net Normal file
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@ -0,0 +1,85 @@
(export (version "E")
(design
(source "/home/mike/Projects/src/kicad/qa/data/eeschema/netlists/legacy_power/legacy_power.kicad_sch")
(date "Mon 20 Feb 2023 10:37:01 AM EST")
(tool "Eeschema 6.0.10-86aedd382b~118~ubuntu22.10.1")
(sheet (number "1") (name "/") (tstamps "/")
(title_block
(title)
(company)
(rev)
(date)
(source "legacy_power.kicad_sch")
(comment (number "1") (value ""))
(comment (number "2") (value ""))
(comment (number "3") (value ""))
(comment (number "4") (value ""))
(comment (number "5") (value ""))
(comment (number "6") (value ""))
(comment (number "7") (value ""))
(comment (number "8") (value ""))
(comment (number "9") (value "")))))
(components
(comp (ref "D1001")
(value "LED")
(libsource (lib "Device") (part "LED") (description "Light emitting diode"))
(property (name "Sheetname") (value ""))
(property (name "Sheetfile") (value "legacy_power.kicad_sch"))
(sheetpath (names "/") (tstamps "/"))
(tstamps "e3eceee5-b863-4693-8411-20a6d0dcce37"))
(comp (ref "U1001")
(value "74AHC1G00")
(datasheet "http://www.ti.com/lit/sg/scyt129e/scyt129e.pdf")
(libsource (lib "74xGxx") (part "74AHC1G00") (description "Single NAND Gate, Low-Voltage CMOS"))
(property (name "Sheetname") (value ""))
(property (name "Sheetfile") (value "legacy_power.kicad_sch"))
(sheetpath (names "/") (tstamps "/"))
(tstamps "801334a8-b16d-4581-b41c-57060138b236")))
(libparts
(libpart (lib "74xGxx") (part "74AHC1G00")
(description "Single NAND Gate, Low-Voltage CMOS")
(docs "http://www.ti.com/lit/sg/scyt129e/scyt129e.pdf")
(footprints
(fp "SOT*")
(fp "SG-*"))
(fields
(field (name "Reference") "U")
(field (name "Value") "74AHC1G00")
(field (name "Datasheet") "http://www.ti.com/lit/sg/scyt129e/scyt129e.pdf"))
(pins
(pin (num "1") (name "") (type "input"))
(pin (num "2") (name "") (type "input"))
(pin (num "3") (name "GND") (type "power_in"))
(pin (num "4") (name "") (type "output"))
(pin (num "5") (name "VCC") (type "power_in"))))
(libpart (lib "Device") (part "LED")
(description "Light emitting diode")
(docs "~")
(footprints
(fp "LED*")
(fp "LED_SMD:*")
(fp "LED_THT:*"))
(fields
(field (name "Reference") "D")
(field (name "Value") "LED")
(field (name "Datasheet") "~"))
(pins
(pin (num "1") (name "K") (type "passive"))
(pin (num "2") (name "A") (type "passive")))))
(libraries
(library (logical "74xGxx")
(uri "/usr/share/kicad/symbols//74xGxx.kicad_sym"))
(library (logical "Device")
(uri "/usr/share/kicad/symbols//Device.kicad_sym")))
(nets
(net (code "1") (name "+3.3V")
(node (ref "U1001") (pin "2") (pintype "input")))
(net (code "2") (name "GND")
(node (ref "D1001") (pin "1") (pinfunction "K") (pintype "passive"))
(node (ref "U1001") (pin "3") (pinfunction "GND") (pintype "power_in")))
(net (code "3") (name "Net-(D1001-Pad2)")
(node (ref "D1001") (pin "2") (pinfunction "A") (pintype "passive"))
(node (ref "U1001") (pin "4") (pintype "output")))
(net (code "4") (name "VCC")
(node (ref "U1001") (pin "1") (pintype "input"))
(node (ref "U1001") (pin "5") (pinfunction "VCC") (pintype "power_in")))))

3
qa/data/eeschema/netlists/legacy_power4/legacy_power4-cache.dcm Executable file
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@ -0,0 +1,3 @@
EESchema-DOCLIB Version 2.0
#
#End Doc Library

51
qa/data/eeschema/netlists/legacy_power4/legacy_power4-cache.lib Executable file
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@ -0,0 +1,51 @@
EESchema-LIBRARY Version 2.3
#encoding utf-8
#
# +3V3
#
DEF +3V3 #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -150 50 H I C CNN
F1 "+3V3" 0 140 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
ALIAS +3.3V
DRAW
P 2 0 1 0 -30 50 0 100 N
P 2 0 1 0 0 0 0 100 N
P 2 0 1 0 0 100 30 50 N
X VCC 1 0 0 0 U 50 50 1 1 W N
ENDDRAW
ENDDEF
#
# GND
#
DEF GND #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -250 50 H I C CNN
F1 "GND" 0 -150 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N
X GND 1 0 0 0 D 50 50 1 1 W N
ENDDRAW
ENDDEF
#
# R
#
DEF R R 0 0 N Y 1 F N
F0 "R" 80 0 50 V V C CNN
F1 "R" 0 0 50 V V C CNN
F2 "" -70 0 50 V I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
R_*
R_*
$ENDFPLIST
DRAW
S -40 -100 40 100 0 1 10 N
X ~ 1 0 150 50 D 50 50 1 1 P
X ~ 2 0 -150 50 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
#End Library

qa/data/eeschema/netlists/legacy_power4/legacy_power4.kicad_pcb
Executable file
View File

LOADING design file

48
qa/data/eeschema/netlists/legacy_power4/legacy_power4.net Executable file
View File

@ -0,0 +1,48 @@
(export (version D)
(design
(source Z:/legacy_power4/legacy_power4.sch)
(date "2/22/2023 9:37:06 AM")
(tool "Eeschema 4.0.7")
(sheet (number 1) (name /) (tstamps /)
(title_block
(title)
(company)
(rev)
(date)
(source legacy_power4.sch)
(comment (number 1) (value ""))
(comment (number 2) (value ""))
(comment (number 3) (value ""))
(comment (number 4) (value "")))))
(components
(comp (ref R1)
(value R)
(libsource (lib symbols) (part R))
(sheetpath (names /) (tstamps /))
(tstamp 63F628CC))
(comp (ref R2)
(value R)
(libsource (lib symbols) (part R))
(sheetpath (names /) (tstamps /))
(tstamp 63F6292B)))
(libparts
(libpart (lib symbols) (part R)
(footprints
(fp R_*)
(fp R_*))
(fields
(field (name Reference) R)
(field (name Value) R))
(pins
(pin (num 1) (name ~) (type passive))
(pin (num 2) (name ~) (type passive)))))
(libraries
(library (logical symbols)
(uri Z:\legacy_power4\symbols.lib)))
(nets
(net (code 1) (name VCC)
(node (ref R1) (pin 1))
(node (ref R2) (pin 1)))
(net (code 2) (name GND)
(node (ref R1) (pin 2))
(node (ref R2) (pin 2)))))

32
qa/data/eeschema/netlists/legacy_power4/legacy_power4.pro Executable file
View File

@ -0,0 +1,32 @@
update=2/22/2023 9:36:23 AM
version=1
last_client=kicad
[pcbnew]
version=1
LastNetListRead=
UseCmpFile=1
PadDrill=0.600000000000
PadDrillOvalY=0.600000000000
PadSizeH=1.500000000000
PadSizeV=1.500000000000
PcbTextSizeV=1.500000000000
PcbTextSizeH=1.500000000000
PcbTextThickness=0.300000000000
ModuleTextSizeV=1.000000000000
ModuleTextSizeH=1.000000000000
ModuleTextSizeThickness=0.150000000000
SolderMaskClearance=0.000000000000
SolderMaskMinWidth=0.000000000000
DrawSegmentWidth=0.200000000000
BoardOutlineThickness=0.100000000000
ModuleOutlineThickness=0.150000000000
[cvpcb]
version=1
NetIExt=net
[general]
version=1
[eeschema]
version=1
LibDir=
[eeschema/libraries]
LibName1=symbols

86
qa/data/eeschema/netlists/legacy_power4/legacy_power4.sch Executable file
View File

@ -0,0 +1,86 @@
EESchema Schematic File Version 2
LIBS:symbols
LIBS:legacy_power4-cache
EELAYER 25 0
EELAYER END
$Descr A4 11693 8268
encoding utf-8
Sheet 1 1
Title ""
Date ""
Rev ""
Comp ""
Comment1 ""
Comment2 ""
Comment3 ""
Comment4 ""
$EndDescr
Text Notes 2850 1650 0 60 ~ 0
Actually VCC, see hidden pin.
$Comp
L +3.3V #PWR01
U 1 1 63F628AD
P 3100 1900
F 0 "#PWR01" H 3100 1750 50 0001 C CNN
F 1 "+3.3V" H 3100 2040 50 0000 C CNN
F 2 "" H 3100 1900 50 0001 C CNN
F 3 "" H 3100 1900 50 0001 C CNN
1 3100 1900
1 0 0 -1
$EndComp
$Comp
L +3.3V #PWR02
U 1 1 63F628BF
P 3450 1900
F 0 "#PWR02" H 3450 1750 50 0001 C CNN
F 1 "+3.3V" H 3450 2040 50 0000 C CNN
F 2 "" H 3450 1900 50 0001 C CNN
F 3 "" H 3450 1900 50 0001 C CNN
1 3450 1900
1 0 0 -1
$EndComp
$Comp
L R R1
U 1 1 63F628CC
P 3100 2050
F 0 "R1" V 3180 2050 50 0000 C CNN
F 1 "R" V 3100 2050 50 0000 C CNN
F 2 "" V 3030 2050 50 0001 C CNN
F 3 "" H 3100 2050 50 0001 C CNN
1 3100 2050
1 0 0 -1
$EndComp
$Comp
L R R2
U 1 1 63F6292B
P 3450 2050
F 0 "R2" V 3530 2050 50 0000 C CNN
F 1 "R" V 3450 2050 50 0000 C CNN
F 2 "" V 3380 2050 50 0001 C CNN
F 3 "" H 3450 2050 50 0001 C CNN
1 3450 2050
1 0 0 -1
$EndComp
$Comp
L GND #PWR03
U 1 1 63F6294F
P 3100 2200
F 0 "#PWR03" H 3100 1950 50 0001 C CNN
F 1 "GND" H 3100 2050 50 0000 C CNN
F 2 "" H 3100 2200 50 0001 C CNN
F 3 "" H 3100 2200 50 0001 C CNN
1 3100 2200
1 0 0 -1
$EndComp
$Comp
L GND #PWR04
U 1 1 63F62967
P 3450 2200
F 0 "#PWR04" H 3450 1950 50 0001 C CNN
F 1 "GND" H 3450 2050 50 0000 C CNN
F 2 "" H 3450 2200 50 0001 C CNN
F 3 "" H 3450 2200 50 0001 C CNN
1 3450 2200
1 0 0 -1
$EndComp
$EndSCHEMATC

3
qa/data/eeschema/netlists/legacy_power4/symbols.dcm Executable file
View File

@ -0,0 +1,3 @@
EESchema-DOCLIB Version 2.0
#
#End Doc Library

51
qa/data/eeschema/netlists/legacy_power4/symbols.lib Executable file
View File

@ -0,0 +1,51 @@
EESchema-LIBRARY Version 2.3
#encoding utf-8
#
# +3V3
#
DEF +3V3 #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -150 50 H I C CNN
F1 "+3V3" 0 140 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
ALIAS +3.3V
DRAW
P 2 0 1 0 -30 50 0 100 N
P 2 0 1 0 0 0 0 100 N
P 2 0 1 0 0 100 30 50 N
X VCC 1 0 0 0 U 50 50 1 1 W N
ENDDRAW
ENDDEF
#
# GND
#
DEF GND #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -250 50 H I C CNN
F1 "GND" 0 -150 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N
X GND 1 0 0 0 D 50 50 1 1 W N
ENDDRAW
ENDDEF
#
# R
#
DEF R R 0 0 N Y 1 F N
F0 "R" 80 0 50 V V C CNN
F1 "R" 0 0 50 V V C CNN
F2 "" -70 0 50 V I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
R_*
R_*
$ENDFPLIST
DRAW
S -40 -100 40 100 0 1 10 N
X ~ 1 0 150 50 D 50 50 1 1 P
X ~ 2 0 -150 50 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
#End Library

3
qa/schematic_utils/schematic_file_util.cpp
View File

@ -184,6 +184,9 @@ void LoadSchematic( SETTINGS_MANAGER& aSettingsManager, const wxString& aRelPath
sheets.UpdateSymbolInstanceData( aSchematic->RootScreen()->GetSymbolInstances() );
sheets.UpdateSheetInstanceData( aSchematic->RootScreen()->GetSheetInstances() );
if( aSchematic->RootScreen()->GetFileFormatVersionAtLoad() < 20230221 )
screens.FixLegacyPowerSymbolMismatches();
if( aSchematic->RootScreen()->GetFileFormatVersionAtLoad() < 20221206 )
{
for( SCH_SCREEN* screen = screens.GetFirst(); screen; screen = screens.GetNext() )

1
qa/unittests/eeschema/CMakeLists.txt
View File

@ -78,6 +78,7 @@ set( QA_EESCHEMA_SRCS
test_netlist_exporter_kicad.cpp
test_netlist_exporter_spice.cpp
test_ee_item.cpp
test_legacy_power_symbols.cpp
test_pin_numbers.cpp
test_sch_pin.cpp
test_sch_rtree.cpp

3
qa/unittests/eeschema/eeschema_test_utils.cpp
View File

@ -104,6 +104,9 @@ void KI_TEST::SCHEMATIC_TEST_FIXTURE::LoadSchematic( const wxString& aBaseName )
screen->MigrateSimModels();
}
if( m_schematic.RootScreen()->GetFileFormatVersionAtLoad() < 20230221 )
screens.FixLegacyPowerSymbolMismatches();
sheets.AnnotatePowerSymbols();
// NOTE: This is required for multi-unit symbols to be correct

73
qa/unittests/eeschema/test_legacy_power_symbols.cpp Normal file
View File

@ -0,0 +1,73 @@
/*
* This program source code file is part of KiCad, a free EDA CAD application.
*
* Copyright (C) 2023 KiCad Developers, see AUTHORS.TXT for contributors.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 3
* of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, you may find one at
* http://www.gnu.org/licenses/
*/
#include <qa_utils/wx_utils/unit_test_utils.h>
#include <schematic_utils/schematic_file_util.h>
#include <connection_graph.h>
#include <schematic.h>
#include <sch_screen.h>
#include <settings/settings_manager.h>
#include <locale_io.h>
struct LEGACY_POWER_SYMBOLS_TEST_FIXTURE
{
LEGACY_POWER_SYMBOLS_TEST_FIXTURE() :
m_settingsManager( true /* headless */ )
{ }
void CheckSymbols()
{
for( SCH_ITEM* item : m_schematic->RootScreen()->Items().OfType( SCH_SYMBOL_T ) )
{
SCH_SYMBOL* symbol = static_cast<SCH_SYMBOL*>( item );
// Fix pre-8.0 legacy power symbols with invisible pins
// that have mismatched pin names and value fields
if( symbol->GetLibSymbolRef()
&& symbol->GetLibSymbolRef()->IsPower()
&& symbol->GetAllLibPins().size() > 0
&& symbol->GetAllLibPins()[0]->IsGlobalPower()
&& !symbol->GetAllLibPins()[0]->IsVisible() )
{
BOOST_CHECK_EQUAL( symbol->GetValueFieldText(true), symbol->GetAllLibPins()[0]->GetName() );
}
}
}
SETTINGS_MANAGER m_settingsManager;
std::unique_ptr<SCHEMATIC> m_schematic;
};
BOOST_FIXTURE_TEST_CASE( LegacyPowerFixup, LEGACY_POWER_SYMBOLS_TEST_FIXTURE )
{
KI_TEST::LoadSchematic( m_settingsManager, "netlists/legacy_power/legacy_power", m_schematic );
CheckSymbols();
}
BOOST_FIXTURE_TEST_CASE( LegacyPower4Fixup, LEGACY_POWER_SYMBOLS_TEST_FIXTURE )
{
KI_TEST::LoadSchematic( m_settingsManager, "netlists/legacy_power/legacy_power", m_schematic );
CheckSymbols();
}

10
qa/unittests/eeschema/test_netlists.cpp
View File

@ -171,4 +171,14 @@ BOOST_AUTO_TEST_CASE( BusEntries )
doNetlistTest( "bus_entries" );
}
BOOST_AUTO_TEST_CASE( LegacyPower )
{
doNetlistTest( "legacy_power" );
}
BOOST_AUTO_TEST_CASE( LegacyPower4 )
{
doNetlistTest( "legacy_power4" );
}
BOOST_AUTO_TEST_SUITE_END()