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Implement PTH/NPTH/courtyard collision tests.

Browse Source 
Fixes https://gitlab.com/kicad/code/kicad/issues/9081
This commit is contained in:
Jeff Young 2021-09-04 00:16:05 +01:00
parent 1fe4aaa64f
commit a397e85589
4 changed files with 713 additions and 8 deletions

69
pcbnew/drc/drc_test_provider_courtyard_clearance.cpp
View File

@ -25,6 +25,8 @@
#include <drc/drc_engine.h>
#include <drc/drc_item.h>
#include <drc/drc_rule.h>
#include <pad.h>
#include <geometry/shape_segment.h>
#include <drc/drc_test_provider_clearance_base.h>
#include <footprint.h>
@ -34,6 +36,8 @@
- DRCE_OVERLAPPING_FOOTPRINTS
- DRCE_MISSING_COURTYARD
- DRCE_MALFORMED_COURTYARD
- DRCE_PTH_IN_COURTYARD,
- DRCE_NPTH_IN_COURTYARD,
TODO: do an actual clearance check instead of polygon intersection. Treat closed outlines
as filled and allow open curves in the courtyard.
@ -145,9 +149,6 @@ bool DRC_TEST_PROVIDER_COURTYARD_CLEARANCE::testCourtyardClearances()
{
const int delta = 100; // This is the number of tests between 2 calls to the progress bar
if( m_drcEngine->IsErrorLimitExceeded( DRCE_OVERLAPPING_FOOTPRINTS) )
return true; // continue with other tests
if( !reportPhase( _( "Checking footprints for overlapping courtyards..." ) ) )
return false; // DRC cancelled
@ -158,15 +159,24 @@ bool DRC_TEST_PROVIDER_COURTYARD_CLEARANCE::testCourtyardClearances()
if( !reportProgress( ii++, m_board->Footprints().size(), delta ) )
return false; // DRC cancelled
if( m_drcEngine->IsErrorLimitExceeded( DRCE_OVERLAPPING_FOOTPRINTS) )
break;
if( m_drcEngine->IsErrorLimitExceeded( DRCE_OVERLAPPING_FOOTPRINTS)
&& m_drcEngine->IsErrorLimitExceeded( DRCE_PTH_IN_COURTYARD )
&& m_drcEngine->IsErrorLimitExceeded( DRCE_NPTH_IN_COURTYARD ) )
{
return true; // continue with other tests
}
FOOTPRINT* fpA = *itA;
const SHAPE_POLY_SET& frontA = fpA->GetPolyCourtyard( F_CrtYd );
const SHAPE_POLY_SET& backA = fpA->GetPolyCourtyard( B_CrtYd );
if( frontA.OutlineCount() == 0 && backA.OutlineCount() == 0 )
continue; // No courtyards defined
if( frontA.OutlineCount() == 0 && backA.OutlineCount() == 0
&& m_drcEngine->IsErrorLimitExceeded( DRCE_PTH_IN_COURTYARD )
&& m_drcEngine->IsErrorLimitExceeded( DRCE_NPTH_IN_COURTYARD ) )
{
// No courtyards defined and no hole testing against other footprint's courtyards
continue;
}
BOX2I frontBBox = frontA.BBoxFromCaches();
BOX2I backBBox = backA.BBoxFromCaches();
@ -174,9 +184,12 @@ bool DRC_TEST_PROVIDER_COURTYARD_CLEARANCE::testCourtyardClearances()
frontBBox.Inflate( m_largestClearance );
backBBox.Inflate( m_largestClearance );
EDA_RECT fpABBox = fpA->GetBoundingBox();
for( auto itB = itA + 1; itB != m_board->Footprints().end(); itB++ )
{
FOOTPRINT* fpB = *itB;
EDA_RECT fpBBBox = fpB->GetBoundingBox();
const SHAPE_POLY_SET& frontB = fpB->GetPolyCourtyard( F_CrtYd );
const SHAPE_POLY_SET& backB = fpB->GetPolyCourtyard( B_CrtYd );
DRC_CONSTRAINT constraint;
@ -237,6 +250,48 @@ bool DRC_TEST_PROVIDER_COURTYARD_CLEARANCE::testCourtyardClearances()
reportViolation( drce, (wxPoint) pos );
}
}
auto testPadAgainstCourtyards =
[&]( const PAD* pad, const FOOTPRINT* footprint )
{
int errorCode = 0;
if( pad->GetAttribute() == PAD_ATTRIB::PTH )
errorCode = DRCE_PTH_IN_COURTYARD;
else if( pad->GetAttribute() == PAD_ATTRIB::NPTH )
errorCode = DRCE_NPTH_IN_COURTYARD;
else
return;
if( m_drcEngine->IsErrorLimitExceeded( errorCode ) )
return;
const SHAPE_SEGMENT* hole = pad->GetEffectiveHoleShape();
const SHAPE_POLY_SET& front = footprint->GetPolyCourtyard( F_CrtYd );
const SHAPE_POLY_SET& back = footprint->GetPolyCourtyard( B_CrtYd );
if( ( front.OutlineCount() > 0 && front.Collide( hole, 0 ) )
|| ( back.OutlineCount() > 0 && back.Collide( hole, 0 ) ) )
{
std::shared_ptr<DRC_ITEM> drce = DRC_ITEM::Create( errorCode );
drce->SetItems( pad, footprint );
reportViolation( drce, pad->GetPosition() );
}
};
if( ( frontA.OutlineCount() > 0 && frontA.BBoxFromCaches().Intersects( fpBBBox ) )
|| ( backA.OutlineCount() > 0 && backA.BBoxFromCaches().Intersects( fpBBBox ) ) )
{
for( const PAD* padB : fpB->Pads() )
testPadAgainstCourtyards( padB, fpA );
}
if( ( frontB.OutlineCount() > 0 && frontB.BBoxFromCaches().Intersects( fpABBox ) )
|| ( backB.OutlineCount() > 0 && backB.BBoxFromCaches().Intersects( fpABBox ) ) )
{
for( const PAD* padA : fpA->Pads() )
testPadAgainstCourtyards( padA, fpB );
}
}
}

qa/data/issue9081.kicad_pcb
Normal file
View File

LOADING design file

434
qa/data/issue9081.kicad_pro Normal file
View File

@ -0,0 +1,434 @@
{
"board": {
"design_settings": {
"defaults": {
"board_outline_line_width": 0.09999999999999999,
"copper_line_width": 0.19999999999999998,
"copper_text_italic": false,
"copper_text_size_h": 1.5,
"copper_text_size_v": 1.5,
"copper_text_thickness": 0.3,
"copper_text_upright": false,
"courtyard_line_width": 0.049999999999999996,
"dimension_precision": 4,
"dimension_units": 3,
"dimensions": {
"arrow_length": 1270000,
"extension_offset": 500000,
"keep_text_aligned": true,
"suppress_zeroes": false,
"text_position": 0,
"units_format": 1
},
"fab_line_width": 0.09999999999999999,
"fab_text_italic": false,
"fab_text_size_h": 1.0,
"fab_text_size_v": 1.0,
"fab_text_thickness": 0.15,
"fab_text_upright": false,
"other_line_width": 0.15,
"other_text_italic": false,
"other_text_size_h": 1.0,
"other_text_size_v": 1.0,
"other_text_thickness": 0.15,
"other_text_upright": false,
"pads": {
"drill": 0.762,
"height": 1.524,
"width": 1.524
},
"silk_line_width": 0.15,
"silk_text_italic": false,
"silk_text_size_h": 1.0,
"silk_text_size_v": 1.0,
"silk_text_thickness": 0.15,
"silk_text_upright": false,
"zones": {
"45_degree_only": false,
"min_clearance": 0.508
}
},
"diff_pair_dimensions": [
{
"gap": 0.0,
"via_gap": 0.0,
"width": 0.0
}
],
"drc_exclusions": [],
"meta": {
"version": 2
},
"rule_severities": {
"annular_width": "error",
"clearance": "error",
"copper_edge_clearance": "error",
"courtyards_overlap": "error",
"diff_pair_gap_out_of_range": "error",
"diff_pair_uncoupled_length_too_long": "error",
"drill_out_of_range": "error",
"duplicate_footprints": "warning",
"extra_footprint": "warning",
"hole_clearance": "error",
"hole_near_hole": "error",
"invalid_outline": "error",
"item_on_disabled_layer": "error",
"items_not_allowed": "error",
"length_out_of_range": "error",
"malformed_courtyard": "error",
"microvia_drill_out_of_range": "error",
"missing_courtyard": "ignore",
"missing_footprint": "warning",
"net_conflict": "warning",
"npth_inside_courtyard": "error",
"padstack": "error",
"pth_inside_courtyard": "error",
"shorting_items": "error",
"silk_over_copper": "warning",
"silk_overlap": "warning",
"skew_out_of_range": "error",
"too_many_vias": "error",
"track_dangling": "warning",
"track_width": "error",
"tracks_crossing": "error",
"unconnected_items": "error",
"unresolved_variable": "error",
"via_dangling": "warning",
"zone_has_empty_net": "error",
"zones_intersect": "error"
},
"rules": {
"allow_blind_buried_vias": false,
"allow_microvias": false,
"max_error": 0.005,
"min_clearance": 0.0,
"min_copper_edge_clearance": 0.0,
"min_hole_clearance": 0.0,
"min_hole_to_hole": 0.25,
"min_microvia_diameter": 0.19999999999999998,
"min_microvia_drill": 0.09999999999999999,
"min_silk_clearance": 0.0,
"min_through_hole_diameter": 0.3,
"min_track_width": 0.19999999999999998,
"min_via_annular_width": 0.049999999999999996,
"min_via_diameter": 0.39999999999999997,
"solder_mask_clearance": 0.0,
"solder_mask_min_width": 0.0,
"use_height_for_length_calcs": true
},
"track_widths": [
0.0
],
"via_dimensions": [
{
"diameter": 0.0,
"drill": 0.0
}
],
"zones_allow_external_fillets": false,
"zones_use_no_outline": true
},
"layer_presets": []
},
"boards": [],
"cvpcb": {
"equivalence_files": []
},
"erc": {
"erc_exclusions": [],
"meta": {
"version": 0
},
"pin_map": [
[
0,
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],
[
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[
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]
],
"rule_severities": {
"bus_definition_conflict": "error",
"bus_entry_needed": "error",
"bus_label_syntax": "error",
"bus_to_bus_conflict": "error",
"bus_to_net_conflict": "error",
"different_unit_footprint": "error",
"different_unit_net": "error",
"duplicate_reference": "error",
"duplicate_sheet_names": "error",
"extra_units": "error",
"global_label_dangling": "warning",
"hier_label_mismatch": "error",
"label_dangling": "error",
"lib_symbol_issues": "warning",
"multiple_net_names": "warning",
"net_not_bus_member": "warning",
"no_connect_connected": "warning",
"no_connect_dangling": "warning",
"pin_not_connected": "error",
"pin_not_driven": "error",
"pin_to_pin": "warning",
"power_pin_not_driven": "error",
"similar_labels": "warning",
"unannotated": "error",
"unit_value_mismatch": "error",
"unresolved_variable": "error",
"wire_dangling": "error"
}
},
"libraries": {
"pinned_footprint_libs": [],
"pinned_symbol_libs": []
},
"meta": {
"filename": "asdf_DRC_THThole_5.99.kicad_pro",
"version": 1
},
"net_settings": {
"classes": [
{
"bus_width": 12.0,
"clearance": 0.2,
"diff_pair_gap": 0.25,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.2,
"line_style": 0,
"microvia_diameter": 0.3,
"microvia_drill": 0.1,
"name": "Default",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.25,
"via_diameter": 0.8,
"via_drill": 0.4,
"wire_width": 6.0
}
],
"meta": {
"version": 0
},
"net_colors": null
},
"pcbnew": {
"last_paths": {
"gencad": "",
"idf": "",
"netlist": "",
"specctra_dsn": "",
"step": "",
"vrml": ""
},
"page_layout_descr_file": ""
},
"schematic": {
"annotate_start_num": 0,
"drawing": {
"default_bus_thickness": 12.0,
"default_junction_size": 40.0,
"default_line_thickness": 6.0,
"default_text_size": 50.0,
"default_wire_thickness": 6.0,
"field_names": [],
"intersheets_ref_own_page": false,
"intersheets_ref_prefix": "",
"intersheets_ref_short": false,
"intersheets_ref_show": false,
"intersheets_ref_suffix": "",
"junction_size_choice": 3,
"label_size_ratio": 0.375,
"pin_symbol_size": 25.0,
"text_offset_ratio": 0.15
},
"legacy_lib_dir": "",
"legacy_lib_list": [],
"meta": {
"version": 1
},
"net_format_name": "",
"ngspice": {
"fix_include_paths": true,
"fix_passive_vals": false,
"meta": {
"version": 0
},
"model_mode": 0,
"workbook_filename": ""
},
"page_layout_descr_file": "",
"plot_directory": "",
"spice_adjust_passive_values": false,
"spice_external_command": "spice \"%I\"",
"subpart_first_id": 65,
"subpart_id_separator": 0
},
"sheets": [
[
"f1329f92-898b-48fb-8d8c-becaafb4793f",
""
]
],
"text_variables": {}
}

3
qa/pcbnew/drc/test_drc_regressions.cpp
View File

@ -111,7 +111,8 @@ BOOST_FIXTURE_TEST_CASE( DRCFalseNegativeRegressions, DRC_REGRESSION_TEST_FIXTUR
{ "issue7241", 1 },
{ "issue7267", 4 },
{ "issue7325", 2 },
{ "issue8003", 2 } };
{ "issue8003", 2 },
{ "issue9081", 2 } };
for( const std::pair<wxString, int>& entry : tests )
{