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Fix up Annular ring check

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- Remove bespoke collide routine.  We should never rewrite these instead
  of using the geometry library
- Optimize check by creating unified geometry before colliding
- Make extra variable that we don't need but makes cherry-picks easier
  (min/maxAnnularWidth)

Fixes https://gitlab.com/kicad/code/kicad/-/issues/19325
This commit is contained in:
Seth Hillbrand 2024-12-22 14:48:48 -08:00
parent d38bda4d53
commit a611c72c27
5 changed files with 666 additions and 148 deletions

164
pcbnew/drc/drc_test_provider_annular_width.cpp
View File

@ -44,107 +44,6 @@
- pad stack support (different IAR/OAR values depending on layer)
*/
/**
* Find the nearest collision point between two shape line chains.
*
* @note This collision test only tests the shape line chain segments (outline) by setting the
* shape closed status to false.
*
* @param aLhs is the left hand shape line chain to run the collision test on.
* @param aRhs is the right hand shape line chain the run the collision test against \a aLhs.
* @param aClearance is the collision clearance between the two shape line changes.
* @param[out] aDistance is an optional pointer to store the nearest collision distance.
* @param[out] aPt1 is an optional pointer to store the nearest collision point.
* @retrun true if a collision occurs between \a aLhs and \a aRhs otherwise false.
*/
static inline bool collide( const SHAPE_LINE_CHAIN& aLhs, const SHAPE_LINE_CHAIN& aRhs,
int aClearance, int* aDistance = nullptr, VECTOR2I* aPt1 = nullptr )
{
wxCHECK( aLhs.PointCount() && aRhs.PointCount(), false );
VECTOR2I pt1;
bool retv = false;
int dist = std::numeric_limits<int>::max();
int tmp = dist;
SHAPE_LINE_CHAIN lhs( aLhs );
SHAPE_LINE_CHAIN rhs( aRhs );
lhs.SetClosed( false );
lhs.Append( lhs.CPoint( 0 ) );
rhs.SetClosed( false );
rhs.Append( rhs.CPoint( 0 ) );
for( int i = 0; i < rhs.SegmentCount(); i ++ )
{
if( lhs.Collide( rhs.CSegment( i ), tmp, &tmp, &pt1 ) )
{
retv = true;
if( tmp < dist )
dist = tmp;
if( aDistance )
*aDistance = dist;
if( aPt1 )
*aPt1 = pt1;
}
}
return retv;
}
static bool collide( const SHAPE_POLY_SET& aLhs, const SHAPE_LINE_CHAIN& aRhs, int aClearance,
int* aDistance = nullptr, VECTOR2I* aPt1 = nullptr )
{
VECTOR2I pt1;
bool retv = false;
int tmp = std::numeric_limits<int>::max();
int dist = tmp;
for( int i = 0; i < aLhs.OutlineCount(); i++ )
{
if( collide( aLhs.Outline( i ), aRhs, aClearance, &tmp, &pt1 ) )
{
retv = true;
if( tmp < dist )
{
dist = tmp;
if( aDistance )
*aDistance = dist;
if( aPt1 )
*aPt1 = pt1;
}
}
for( int j = 0; j < aLhs.HoleCount( i ); i++ )
{
if( collide( aLhs.CHole( i, j ), aRhs, aClearance, &tmp, &pt1 ) )
{
retv = true;
if( tmp < dist )
{
dist = tmp;
if( aDistance )
*aDistance = dist;
if( aPt1 )
*aPt1 = pt1;
}
}
}
}
return retv;
}
class DRC_TEST_PROVIDER_ANNULAR_WIDTH : public DRC_TEST_PROVIDER
{
@ -246,7 +145,8 @@ bool DRC_TEST_PROVIDER_ANNULAR_WIDTH::Run()
auto constraint = m_drcEngine->EvalRules( ANNULAR_WIDTH_CONSTRAINT, item, nullptr,
UNDEFINED_LAYER );
int annularWidth = 0;
int minAnnularWidth = INT_MAX;
int maxAnnularWidth = 0;
int v_min = 0;
int v_max = 0;
bool fail_min = false;
@ -258,7 +158,9 @@ bool DRC_TEST_PROVIDER_ANNULAR_WIDTH::Run()
case PCB_VIA_T:
{
PCB_VIA* via = static_cast<PCB_VIA*>( item );
annularWidth = ( via->GetWidth() - via->GetDrillValue() ) / 2;
int annularWidth = ( via->GetWidth() - via->GetDrillValue() ) / 2;
minAnnularWidth = std::min( minAnnularWidth, annularWidth );
maxAnnularWidth = std::max( maxAnnularWidth, annularWidth );
break;
}
@ -266,6 +168,7 @@ bool DRC_TEST_PROVIDER_ANNULAR_WIDTH::Run()
{
PAD* pad = static_cast<PAD*>( item );
bool handled = false;
int annularWidth = 0;
if( !pad->HasHole() || pad->GetAttribute() != PAD_ATTRIB::PTH )
return true;
@ -345,6 +248,7 @@ bool DRC_TEST_PROVIDER_ANNULAR_WIDTH::Run()
&& ( annularWidth < constraint.Value().Min() ) )
{
SHAPE_POLY_SET otherPadOutline;
SHAPE_POLY_SET otherPadHoles;
SHAPE_POLY_SET slotPolygon;
slot->TransformToPolygon( slotPolygon, 0, ERROR_INSIDE );
@ -356,45 +260,47 @@ bool DRC_TEST_PROVIDER_ANNULAR_WIDTH::Run()
UNDEFINED_LAYER, 0, maxError,
ERROR_OUTSIDE );
sameNumPad->TransformHoleToPolygon( otherPadOutline, 0, maxError,
sameNumPad->TransformHoleToPolygon( otherPadHoles, 0, maxError,
ERROR_INSIDE );
}
otherPadOutline.BooleanSubtract( otherPadHoles, SHAPE_POLY_SET::POLYGON_MODE::PM_FAST );
// If the pad hole under test intersects with another pad outline,
// the annular width calculated above is used.
bool intersects = false;
// If the pad hole under test intersects with another pad outline,
// the annular width calculated above is used.
bool intersects = false;
for( int i = 0; i < otherPadOutline.OutlineCount() && !intersects; i++ )
for( int i = 0; i < otherPadOutline.OutlineCount() && !intersects; i++ )
{
intersects |= slotPolygon.COutline( 0 ).Intersects( otherPadOutline.COutline( i ) );
for( int j = 0; j < otherPadOutline.HoleCount( i ) && !intersects; j++ )
{
intersects |= slotPolygon.COutline( 0 ).Intersects( otherPadOutline.COutline( i ) );
if( intersects )
continue;
for( int j = 0; j < otherPadOutline.HoleCount( i ) && !intersects; j++ )
{
intersects |= slotPolygon.COutline( 0 ).Intersects( otherPadOutline.CHole( i, j ) );
if( intersects )
continue;
}
intersects |= slotPolygon.COutline( 0 ).Intersects( otherPadOutline.CHole( i, j ) );
}
}
if( intersects )
continue;
if( !intersects )
{
// Determine the effective annular width if the pad hole under
// test lies withing the boundary of another pad outline.
int effectiveWidth = std::numeric_limits<int>::max();
if( collide( otherPadOutline, slotPolygon.Outline( 0 ),
effectiveWidth, &effectiveWidth ) )
for( int ii = 0; ii < otherPadOutline.OutlineCount(); ii++ )
{
if( effectiveWidth > annularWidth )
annularWidth = effectiveWidth;
if( slot->Collide( &otherPadOutline.Outline( ii ), 0 ) )
{
if( effectiveWidth > annularWidth )
annularWidth = effectiveWidth;
}
}
}
}
}
maxAnnularWidth = std::max( maxAnnularWidth, annularWidth );
minAnnularWidth = std::min( minAnnularWidth, annularWidth );
break;
}
@ -408,13 +314,13 @@ bool DRC_TEST_PROVIDER_ANNULAR_WIDTH::Run()
if( constraint.Value().HasMin() )
{
v_min = constraint.Value().Min();
fail_min = annularWidth < v_min;
fail_min = minAnnularWidth < v_min;
}
if( constraint.Value().HasMax() )
{
v_max = constraint.Value().Max();
fail_max = annularWidth > v_max;
fail_max = maxAnnularWidth > v_max;
}
if( fail_min || fail_max )
@ -427,7 +333,7 @@ bool DRC_TEST_PROVIDER_ANNULAR_WIDTH::Run()
msg = formatMsg( _( "(%s min annular width %s; actual %s)" ),
constraint.GetName(),
v_min,
annularWidth );
minAnnularWidth );
}
if( fail_max )
@ -435,7 +341,7 @@ bool DRC_TEST_PROVIDER_ANNULAR_WIDTH::Run()
msg = formatMsg( _( "(%s max annular width %s; actual %s)" ),
constraint.GetName(),
v_max,
annularWidth );
maxAnnularWidth );
}
drcItem->SetErrorMessage( drcItem->GetErrorText() + wxS( " " ) + msg );

qa/data/pcbnew/issue19325/issue19325.kicad_pcb
Normal file
View File

LOADING design file

273
qa/data/pcbnew/issue19325/issue19325.kicad_pro Normal file
View File

@ -0,0 +1,273 @@
{
"board": {
"3dviewports": [],
"design_settings": {
"defaults": {
"apply_defaults_to_fp_fields": false,
"apply_defaults_to_fp_shapes": false,
"apply_defaults_to_fp_text": false,
"board_outline_line_width": 0.05,
"copper_line_width": 0.2,
"copper_text_italic": false,
"copper_text_size_h": 1.5,
"copper_text_size_v": 1.5,
"copper_text_thickness": 0.3,
"copper_text_upright": false,
"courtyard_line_width": 0.05,
"dimension_precision": 4,
"dimension_units": 3,
"dimensions": {
"arrow_length": 1270000,
"extension_offset": 500000,
"keep_text_aligned": true,
"suppress_zeroes": false,
"text_position": 0,
"units_format": 1
},
"fab_line_width": 0.1,
"fab_text_italic": false,
"fab_text_size_h": 1.0,
"fab_text_size_v": 1.0,
"fab_text_thickness": 0.15,
"fab_text_upright": false,
"other_line_width": 0.1,
"other_text_italic": false,
"other_text_size_h": 1.0,
"other_text_size_v": 1.0,
"other_text_thickness": 0.15,
"other_text_upright": false,
"pads": {
"drill": 0.3,
"height": 0.34,
"width": 0.34
},
"silk_line_width": 0.1,
"silk_text_italic": false,
"silk_text_size_h": 1.0,
"silk_text_size_v": 1.0,
"silk_text_thickness": 0.1,
"silk_text_upright": false,
"zones": {
"min_clearance": 0.5
}
},
"diff_pair_dimensions": [],
"drc_exclusions": [],
"meta": {
"version": 2
},
"rule_severities": {
"annular_width": "error",
"clearance": "error",
"connection_width": "warning",
"copper_edge_clearance": "ignore",
"copper_sliver": "warning",
"courtyards_overlap": "error",
"diff_pair_gap_out_of_range": "error",
"diff_pair_uncoupled_length_too_long": "error",
"drill_out_of_range": "error",
"duplicate_footprints": "warning",
"extra_footprint": "warning",
"footprint": "error",
"footprint_symbol_mismatch": "warning",
"footprint_type_mismatch": "ignore",
"hole_clearance": "error",
"hole_near_hole": "ignore",
"holes_co_located": "warning",
"invalid_outline": "error",
"isolated_copper": "warning",
"item_on_disabled_layer": "error",
"items_not_allowed": "error",
"length_out_of_range": "error",
"lib_footprint_issues": "warning",
"lib_footprint_mismatch": "warning",
"malformed_courtyard": "error",
"microvia_drill_out_of_range": "error",
"missing_courtyard": "ignore",
"missing_footprint": "warning",
"net_conflict": "warning",
"npth_inside_courtyard": "ignore",
"padstack": "warning",
"pth_inside_courtyard": "ignore",
"shorting_items": "error",
"silk_edge_clearance": "ignore",
"silk_over_copper": "ignore",
"silk_overlap": "warning",
"skew_out_of_range": "error",
"solder_mask_bridge": "error",
"starved_thermal": "error",
"text_height": "warning",
"text_thickness": "warning",
"through_hole_pad_without_hole": "error",
"too_many_vias": "error",
"track_dangling": "warning",
"track_width": "error",
"tracks_crossing": "error",
"unconnected_items": "error",
"unresolved_variable": "error",
"via_dangling": "warning",
"zones_intersect": "error"
},
"rules": {
"max_error": 0.005,
"min_clearance": 0.0,
"min_connection": 0.0,
"min_copper_edge_clearance": 0.5,
"min_hole_clearance": 0.25,
"min_hole_to_hole": 0.25,
"min_microvia_diameter": 0.2,
"min_microvia_drill": 0.1,
"min_resolved_spokes": 2,
"min_silk_clearance": 0.0,
"min_text_height": 0.8,
"min_text_thickness": 0.08,
"min_through_hole_diameter": 0.3,
"min_track_width": 0.0,
"min_via_annular_width": 0.1,
"min_via_diameter": 0.5,
"solder_mask_to_copper_clearance": 0.0,
"use_height_for_length_calcs": true
},
"teardrop_options": [
{
"td_onpadsmd": true,
"td_onroundshapesonly": false,
"td_ontrackend": false,
"td_onviapad": true
}
],
"teardrop_parameters": [
{
"td_allow_use_two_tracks": true,
"td_curve_segcount": 0,
"td_height_ratio": 1.0,
"td_length_ratio": 0.5,
"td_maxheight": 2.0,
"td_maxlen": 1.0,
"td_on_pad_in_zone": false,
"td_target_name": "td_round_shape",
"td_width_to_size_filter_ratio": 0.9
},
{
"td_allow_use_two_tracks": true,
"td_curve_segcount": 0,
"td_height_ratio": 1.0,
"td_length_ratio": 0.5,
"td_maxheight": 2.0,
"td_maxlen": 1.0,
"td_on_pad_in_zone": false,
"td_target_name": "td_rect_shape",
"td_width_to_size_filter_ratio": 0.9
},
{
"td_allow_use_two_tracks": true,
"td_curve_segcount": 0,
"td_height_ratio": 1.0,
"td_length_ratio": 0.5,
"td_maxheight": 2.0,
"td_maxlen": 1.0,
"td_on_pad_in_zone": false,
"td_target_name": "td_track_end",
"td_width_to_size_filter_ratio": 0.9
}
],
"track_widths": [],
"tuning_pattern_settings": {
"diff_pair_defaults": {
"corner_radius_percentage": 80,
"corner_style": 1,
"max_amplitude": 1.0,
"min_amplitude": 0.2,
"single_sided": false,
"spacing": 1.0
},
"diff_pair_skew_defaults": {
"corner_radius_percentage": 80,
"corner_style": 1,
"max_amplitude": 1.0,
"min_amplitude": 0.2,
"single_sided": false,
"spacing": 0.6
},
"single_track_defaults": {
"corner_radius_percentage": 80,
"corner_style": 1,
"max_amplitude": 1.0,
"min_amplitude": 0.2,
"single_sided": false,
"spacing": 0.6
}
},
"via_dimensions": [],
"zones_allow_external_fillets": false
},
"ipc2581": {
"dist": "",
"distpn": "",
"internal_id": "",
"mfg": "",
"mpn": ""
},
"layer_presets": [],
"viewports": []
},
"boards": [],
"cvpcb": {
"equivalence_files": []
},
"libraries": {
"pinned_footprint_libs": [],
"pinned_symbol_libs": []
},
"meta": {
"filename": "issue19325.kicad_pro",
"version": 1
},
"net_settings": {
"classes": [
{
"bus_width": 12,
"clearance": 0.2,
"diff_pair_gap": 0.25,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.2,
"line_style": 0,
"microvia_diameter": 0.3,
"microvia_drill": 0.1,
"name": "Default",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.2,
"via_diameter": 0.6,
"via_drill": 0.3,
"wire_width": 6
}
],
"meta": {
"version": 3
},
"net_colors": null,
"netclass_assignments": null,
"netclass_patterns": []
},
"pcbnew": {
"last_paths": {
"gencad": "",
"idf": "",
"netlist": "",
"plot": "",
"pos_files": "",
"specctra_dsn": "",
"step": "",
"svg": "",
"vrml": ""
},
"page_layout_descr_file": ""
},
"schematic": {
"legacy_lib_dir": "",
"legacy_lib_list": []
},
"sheets": [],
"text_variables": {}
}

qa/data/pcbnew/issue19325/issue19325.kicad_sch
Normal file
View File

LOADING design file

39
qa/tests/pcbnew/drc/test_drc_regressions.cpp
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@ -122,26 +122,27 @@ BOOST_FIXTURE_TEST_CASE( DRCFalseNegativeRegressions, DRC_REGRESSION_TEST_FIXTUR
{
// These documents at one time failed to catch DRC errors that they should have
std::vector< std::pair<wxString, int> > tests =
std::vector<std::pair<wxString, int>> tests =
{
{ "issue1358", 2 },
{ "issue2512", 5 },
{ "issue2528", 1 },
{ "issue5750", 4 }, // Shorting zone fills pass DRC in some cases
{ "issue5854", 3 },
{ "issue6879", 6 },
{ "issue6945", 2 },
{ "issue7241", 1 },
{ "issue7267", 5 },
{ "issue7325", 4 },
{ "issue8003", 2 },
{ "issue9081", 2 },
{ "issue12109", 8 }, // Pads fail annular width test
{ "issue14334", 2 }, // Thermal spoke to otherwise unconnected island
{ "issue16566", 6 }, // Pad_Shape vs Shape property
{ "reverse_via", 3 }, // Via/track ordering
{ "intersectingzones", 1 }, // zones are too close to each other
{ "fill_bad", 1 } // zone max BBox was too small
{ "issue1358", 2 },
{ "issue2512", 5 },
{ "issue2528", 1 },
{ "issue5750", 4 }, // Shorting zone fills pass DRC in some cases
{ "issue5854", 3 },
{ "issue6879", 6 },
{ "issue6945", 2 },
{ "issue7241", 1 },
{ "issue7267", 5 },
{ "issue7325", 4 },
{ "issue8003", 2 },
{ "issue9081", 2 },
{ "issue12109", 8 }, // Pads fail annular width test
{ "issue14334", 2 }, // Thermal spoke to otherwise unconnected island
{ "issue16566", 6 }, // Pad_Shape vs Shape property
{ "reverse_via", 3 }, // Via/track ordering
{ "intersectingzones", 1 }, // zones are too close to each other
{ "fill_bad", 1 }, // zone max BBox was too small
{ "issue19325/issue19325", 4 }, // Overlapping pad annular ring calculation
};
for( const auto& [testName, expectedErrors] : tests )