mirror of
https://gitlab.com/kicad/code/kicad.git
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Adding additional demos
Some simulation demos curtesy of Holger Vogt and a new board design curtesy of Pat Deegan
This commit is contained in:
Seth Hillbrand
parent
82a0227c20
commit
d25ac664f8
demos
CMakeLists.txt
simulation
Class-D
analog-multiplier
class-d
AudioDriver.kicad_symClass-D.kicad_proClass-D.kicad_schClass-D.wbkDAudioDriver.libDAudioDriver_os.libsym-lib-table
gain_control
generic_models
power_supplies
LM317_power_supply
1N4002.libLM317.libdiode_bridge.libpower_supply.kicad_propower_supply.kicad_schpower_supply.wbkxformer.lib
boost
GenOpAmp.libPWM.kicad_sympwm2_model.libsmps-com.kicad_prosmps-com.kicad_schsmps-com.wbksym-lib-table
buck_conv
hv_converter
GaN_PSpice_GS-065-018-2-L_L1V3P3.libHSCConverter4.wbkST_SILICON_CARBIDE_SCHOTTKY_V9.LIBhv_converter.cirhv_converter.kicad_prohv_converter.kicad_sch
royer
q17
rectifier
up-down-counter
tiny_tapeout
LICENSE.txtrp2040.kicad_schsym-lib-tabletinytapeout-demo.kicad_pcbtinytapeout-demo.kicad_protinytapeout-demo.kicad_sch
doc
fp-lib-tablepcba
gerber/v0p9p4
tinytapeout-demo-B_Cu.gbrtinytapeout-demo-B_Mask.gbrtinytapeout-demo-B_Paste.gbrtinytapeout-demo-B_Silkscreen.gbrtinytapeout-demo-Edge_Cuts.gbrtinytapeout-demo-F_Cu.gbrtinytapeout-demo-F_Mask.gbrtinytapeout-demo-F_Paste.gbrtinytapeout-demo-F_Silkscreen.gbrtinytapeout-demo-In1_Cu.gbrtinytapeout-demo-In2_Cu.gbrtinytapeout-demo-NPTH.drltinytapeout-demo-PTH.drltinytapeout-demo-User_2.gbrtinytapeout-demo-job.gbrjob
placement
tinytapeout-kicad-libs
3dmodels
footprints
MCU_RaspberryPi_and_Boards.pretty
TinyTapeout.pretty
219-9GULLWING.kicad_mod418121270808.kicad_mod434121025816.kicad_mod632723130112.kicad_modCUI_UJC-HP-3-SMT-TR.kicad_modGCT_USB4500-03-0-A_REVA.kicad_modPinHeader_2x06_P2.54mm_PMODPeriph2B.kicad_modPinSocket_2x06_P2.54mm_PMODHost1A.kicad_modQFN-64-1EP_9x9mm_P0.5mm_EP7.65x7.65mm_REDUCEDPASTE.kicad_modSolderJumper-2_Bridged_Throughole1.kicad_modTT03_BREAKOUT_SMB_FACEDOWN.kicad_modTT04_BREAKOUT_SMB.kicad_modTT_BREAKOUT_PINHEADER_PLACEHOLDER.kicad_modTT_BREAKOUT_PINHEADER_PLACEHOLDER_WITHPAD.kicad_modWL_S7DS-157112V12700.kicad_modWURTH_632723X00011.kicad_mod
ttlib.pretty
symbols
@ -14,6 +14,7 @@ install( DIRECTORY
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stickhub
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test_pads_inside_pads
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test_xil_95108
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tiny_tapeout
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video
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DESTINATION ${KICAD_DEMOS}
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COMPONENT resources
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391
demos/simulation/Class-D/Class-D.kicad_pro
Normal file
391
demos/simulation/Class-D/Class-D.kicad_pro
Normal file
@ -0,0 +1,391 @@
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{
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"board": {
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"3dviewports": [],
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"ipc2581": {
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"dist": "",
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"distpn": "",
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"internal_id": "",
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"mfg": "",
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"mpn": ""
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},
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"layer_presets": [],
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"viewports": []
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},
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"boards": [],
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"cvpcb": {
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"equivalence_files": []
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},
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"erc": {
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"erc_exclusions": [],
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"meta": {
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"version": 0
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},
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"pin_map": [
|
||||
[
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
2
|
||||
],
|
||||
[
|
||||
0,
|
||||
2,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
2,
|
||||
2,
|
||||
2,
|
||||
2
|
||||
],
|
||||
[
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
1,
|
||||
2
|
||||
],
|
||||
[
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
1,
|
||||
1,
|
||||
2,
|
||||
1,
|
||||
1,
|
||||
2
|
||||
],
|
||||
[
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
2
|
||||
],
|
||||
[
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
2
|
||||
],
|
||||
[
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
0,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
2
|
||||
],
|
||||
[
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
2
|
||||
],
|
||||
[
|
||||
0,
|
||||
2,
|
||||
1,
|
||||
2,
|
||||
0,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
2,
|
||||
2,
|
||||
2,
|
||||
2
|
||||
],
|
||||
[
|
||||
0,
|
||||
2,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
2,
|
||||
0,
|
||||
0,
|
||||
2
|
||||
],
|
||||
[
|
||||
0,
|
||||
2,
|
||||
1,
|
||||
1,
|
||||
0,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
2,
|
||||
0,
|
||||
0,
|
||||
2
|
||||
],
|
||||
[
|
||||
2,
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2,
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2,
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2,
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2,
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2,
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2,
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2,
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2,
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2,
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2,
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2
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]
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],
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"rule_severities": {
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"bus_definition_conflict": "error",
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"bus_entry_needed": "error",
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"bus_to_bus_conflict": "error",
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"bus_to_net_conflict": "error",
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"conflicting_netclasses": "error",
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"different_unit_footprint": "error",
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"different_unit_net": "error",
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"duplicate_reference": "error",
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"duplicate_sheet_names": "error",
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"endpoint_off_grid": "warning",
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"extra_units": "error",
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"global_label_dangling": "warning",
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"hier_label_mismatch": "error",
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"label_dangling": "error",
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"lib_symbol_issues": "warning",
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"missing_bidi_pin": "warning",
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"missing_input_pin": "warning",
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"missing_power_pin": "error",
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"missing_unit": "warning",
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"multiple_net_names": "warning",
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"net_not_bus_member": "warning",
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"no_connect_connected": "warning",
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"no_connect_dangling": "warning",
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"pin_not_connected": "error",
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"pin_not_driven": "error",
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"pin_to_pin": "warning",
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"power_pin_not_driven": "error",
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"similar_labels": "warning",
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"simulation_model_issue": "ignore",
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"unannotated": "error",
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"unit_value_mismatch": "error",
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"unresolved_variable": "error",
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"wire_dangling": "error"
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}
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},
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"libraries": {
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"pinned_footprint_libs": [],
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"pinned_symbol_libs": []
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},
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"meta": {
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"filename": "Class-D.kicad_pro",
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"version": 1
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},
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"net_settings": {
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"classes": [
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{
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"bus_width": 12,
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"clearance": 0.2,
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"diff_pair_gap": 0.25,
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"diff_pair_via_gap": 0.25,
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"diff_pair_width": 0.2,
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"line_style": 0,
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"microvia_diameter": 0.3,
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"microvia_drill": 0.1,
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"name": "Default",
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"pcb_color": "rgba(0, 0, 0, 0.000)",
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"schematic_color": "rgba(0, 0, 0, 0.000)",
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"track_width": 0.2,
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"via_diameter": 0.6,
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"via_drill": 0.3,
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"wire_width": 6
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}
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],
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"meta": {
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"version": 3
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},
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"net_colors": null,
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"netclass_assignments": null,
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"netclass_patterns": []
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},
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"pcbnew": {
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"last_paths": {
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"gencad": "",
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"idf": "",
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"netlist": "",
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"plot": "",
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"pos_files": "",
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"specctra_dsn": "",
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"step": "",
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"svg": "",
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"vrml": ""
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},
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"page_layout_descr_file": ""
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},
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"schematic": {
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"annotate_start_num": 0,
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"bom_fmt_presets": [],
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"bom_fmt_settings": {
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"field_delimiter": ",",
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"keep_line_breaks": false,
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"keep_tabs": false,
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"name": "CSV",
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"ref_delimiter": ",",
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"ref_range_delimiter": "",
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"string_delimiter": "\""
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},
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||||
"bom_presets": [],
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||||
"bom_settings": {
|
||||
"exclude_dnp": false,
|
||||
"fields_ordered": [
|
||||
{
|
||||
"group_by": false,
|
||||
"label": "Reference",
|
||||
"name": "Reference",
|
||||
"show": true
|
||||
},
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||||
{
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||||
"group_by": true,
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||||
"label": "Value",
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"name": "Value",
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"show": true
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},
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{
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"group_by": false,
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"label": "Datasheet",
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"name": "Datasheet",
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"show": true
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||||
},
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{
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"group_by": false,
|
||||
"label": "Footprint",
|
||||
"name": "Footprint",
|
||||
"show": true
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||||
},
|
||||
{
|
||||
"group_by": false,
|
||||
"label": "Qty",
|
||||
"name": "${QUANTITY}",
|
||||
"show": true
|
||||
},
|
||||
{
|
||||
"group_by": true,
|
||||
"label": "DNP",
|
||||
"name": "${DNP}",
|
||||
"show": true
|
||||
}
|
||||
],
|
||||
"filter_string": "",
|
||||
"group_symbols": true,
|
||||
"name": "Grouped By Value",
|
||||
"sort_asc": true,
|
||||
"sort_field": "Referenz"
|
||||
},
|
||||
"connection_grid_size": 50.0,
|
||||
"drawing": {
|
||||
"dashed_lines_dash_length_ratio": 12.0,
|
||||
"dashed_lines_gap_length_ratio": 3.0,
|
||||
"default_line_thickness": 6.0,
|
||||
"default_text_size": 50.0,
|
||||
"field_names": [],
|
||||
"intersheets_ref_own_page": false,
|
||||
"intersheets_ref_prefix": "",
|
||||
"intersheets_ref_short": false,
|
||||
"intersheets_ref_show": false,
|
||||
"intersheets_ref_suffix": "",
|
||||
"junction_size_choice": 3,
|
||||
"label_size_ratio": 0.375,
|
||||
"operating_point_overlay_i_precision": 3,
|
||||
"operating_point_overlay_i_range": "~A",
|
||||
"operating_point_overlay_v_precision": 3,
|
||||
"operating_point_overlay_v_range": "~V",
|
||||
"overbar_offset_ratio": 1.23,
|
||||
"pin_symbol_size": 25.0,
|
||||
"text_offset_ratio": 0.15
|
||||
},
|
||||
"legacy_lib_dir": "",
|
||||
"legacy_lib_list": [],
|
||||
"meta": {
|
||||
"version": 1
|
||||
},
|
||||
"net_format_name": "",
|
||||
"ngspice": {
|
||||
"fix_include_paths": true,
|
||||
"meta": {
|
||||
"version": 0
|
||||
},
|
||||
"model_mode": 4,
|
||||
"workbook_filename": "Class-D.wbk"
|
||||
},
|
||||
"page_layout_descr_file": "",
|
||||
"plot_directory": "",
|
||||
"spice_current_sheet_as_root": false,
|
||||
"spice_external_command": "spice \"%I\"",
|
||||
"spice_model_current_sheet_as_root": true,
|
||||
"spice_save_all_currents": false,
|
||||
"spice_save_all_dissipations": false,
|
||||
"spice_save_all_voltages": false,
|
||||
"subpart_first_id": 65,
|
||||
"subpart_id_separator": 0
|
||||
},
|
||||
"sheets": [
|
||||
[
|
||||
"30d43cb8-f82b-4a5d-811a-ca847a6b3021",
|
||||
"Root"
|
||||
]
|
||||
],
|
||||
"text_variables": {}
|
||||
}
|
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391
demos/simulation/analog-multiplier/a-multi.kicad_pro
Normal file
391
demos/simulation/analog-multiplier/a-multi.kicad_pro
Normal file
@ -0,0 +1,391 @@
|
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{
|
||||
"board": {
|
||||
"3dviewports": [],
|
||||
"ipc2581": {
|
||||
"dist": "",
|
||||
"distpn": "",
|
||||
"internal_id": "",
|
||||
"mfg": "",
|
||||
"mpn": ""
|
||||
},
|
||||
"layer_presets": [],
|
||||
"viewports": []
|
||||
},
|
||||
"boards": [],
|
||||
"cvpcb": {
|
||||
"equivalence_files": []
|
||||
},
|
||||
"erc": {
|
||||
"erc_exclusions": [],
|
||||
"meta": {
|
||||
"version": 0
|
||||
},
|
||||
"pin_map": [
|
||||
[
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
2
|
||||
],
|
||||
[
|
||||
0,
|
||||
2,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
2,
|
||||
2,
|
||||
2,
|
||||
2
|
||||
],
|
||||
[
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
1,
|
||||
2
|
||||
],
|
||||
[
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
1,
|
||||
1,
|
||||
2,
|
||||
1,
|
||||
1,
|
||||
2
|
||||
],
|
||||
[
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
2
|
||||
],
|
||||
[
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
2
|
||||
],
|
||||
[
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
0,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
2
|
||||
],
|
||||
[
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
2
|
||||
],
|
||||
[
|
||||
0,
|
||||
2,
|
||||
1,
|
||||
2,
|
||||
0,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
2,
|
||||
2,
|
||||
2,
|
||||
2
|
||||
],
|
||||
[
|
||||
0,
|
||||
2,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
2,
|
||||
0,
|
||||
0,
|
||||
2
|
||||
],
|
||||
[
|
||||
0,
|
||||
2,
|
||||
1,
|
||||
1,
|
||||
0,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
2,
|
||||
0,
|
||||
0,
|
||||
2
|
||||
],
|
||||
[
|
||||
2,
|
||||
2,
|
||||
2,
|
||||
2,
|
||||
2,
|
||||
2,
|
||||
2,
|
||||
2,
|
||||
2,
|
||||
2,
|
||||
2,
|
||||
2
|
||||
]
|
||||
],
|
||||
"rule_severities": {
|
||||
"bus_definition_conflict": "error",
|
||||
"bus_entry_needed": "error",
|
||||
"bus_to_bus_conflict": "error",
|
||||
"bus_to_net_conflict": "error",
|
||||
"conflicting_netclasses": "error",
|
||||
"different_unit_footprint": "error",
|
||||
"different_unit_net": "error",
|
||||
"duplicate_reference": "error",
|
||||
"duplicate_sheet_names": "error",
|
||||
"endpoint_off_grid": "warning",
|
||||
"extra_units": "error",
|
||||
"global_label_dangling": "warning",
|
||||
"hier_label_mismatch": "error",
|
||||
"label_dangling": "error",
|
||||
"lib_symbol_issues": "warning",
|
||||
"missing_bidi_pin": "warning",
|
||||
"missing_input_pin": "warning",
|
||||
"missing_power_pin": "error",
|
||||
"missing_unit": "warning",
|
||||
"multiple_net_names": "warning",
|
||||
"net_not_bus_member": "warning",
|
||||
"no_connect_connected": "warning",
|
||||
"no_connect_dangling": "warning",
|
||||
"pin_not_connected": "error",
|
||||
"pin_not_driven": "error",
|
||||
"pin_to_pin": "warning",
|
||||
"power_pin_not_driven": "error",
|
||||
"similar_labels": "warning",
|
||||
"simulation_model_issue": "ignore",
|
||||
"unannotated": "error",
|
||||
"unit_value_mismatch": "error",
|
||||
"unresolved_variable": "error",
|
||||
"wire_dangling": "error"
|
||||
}
|
||||
},
|
||||
"libraries": {
|
||||
"pinned_footprint_libs": [],
|
||||
"pinned_symbol_libs": []
|
||||
},
|
||||
"meta": {
|
||||
"filename": "a-multi.kicad_pro",
|
||||
"version": 1
|
||||
},
|
||||
"net_settings": {
|
||||
"classes": [
|
||||
{
|
||||
"bus_width": 12,
|
||||
"clearance": 0.2,
|
||||
"diff_pair_gap": 0.25,
|
||||
"diff_pair_via_gap": 0.25,
|
||||
"diff_pair_width": 0.2,
|
||||
"line_style": 0,
|
||||
"microvia_diameter": 0.3,
|
||||
"microvia_drill": 0.1,
|
||||
"name": "Default",
|
||||
"pcb_color": "rgba(0, 0, 0, 0.000)",
|
||||
"schematic_color": "rgba(0, 0, 0, 0.000)",
|
||||
"track_width": 0.2,
|
||||
"via_diameter": 0.6,
|
||||
"via_drill": 0.3,
|
||||
"wire_width": 6
|
||||
}
|
||||
],
|
||||
"meta": {
|
||||
"version": 3
|
||||
},
|
||||
"net_colors": null,
|
||||
"netclass_assignments": null,
|
||||
"netclass_patterns": []
|
||||
},
|
||||
"pcbnew": {
|
||||
"last_paths": {
|
||||
"gencad": "",
|
||||
"idf": "",
|
||||
"netlist": "",
|
||||
"plot": "",
|
||||
"pos_files": "",
|
||||
"specctra_dsn": "",
|
||||
"step": "",
|
||||
"svg": "",
|
||||
"vrml": ""
|
||||
},
|
||||
"page_layout_descr_file": ""
|
||||
},
|
||||
"schematic": {
|
||||
"annotate_start_num": 0,
|
||||
"bom_fmt_presets": [],
|
||||
"bom_fmt_settings": {
|
||||
"field_delimiter": ",",
|
||||
"keep_line_breaks": false,
|
||||
"keep_tabs": false,
|
||||
"name": "CSV",
|
||||
"ref_delimiter": ",",
|
||||
"ref_range_delimiter": "",
|
||||
"string_delimiter": "\""
|
||||
},
|
||||
"bom_presets": [],
|
||||
"bom_settings": {
|
||||
"exclude_dnp": false,
|
||||
"fields_ordered": [
|
||||
{
|
||||
"group_by": false,
|
||||
"label": "Reference",
|
||||
"name": "Reference",
|
||||
"show": true
|
||||
},
|
||||
{
|
||||
"group_by": true,
|
||||
"label": "Value",
|
||||
"name": "Value",
|
||||
"show": true
|
||||
},
|
||||
{
|
||||
"group_by": false,
|
||||
"label": "Datasheet",
|
||||
"name": "Datasheet",
|
||||
"show": true
|
||||
},
|
||||
{
|
||||
"group_by": false,
|
||||
"label": "Footprint",
|
||||
"name": "Footprint",
|
||||
"show": true
|
||||
},
|
||||
{
|
||||
"group_by": false,
|
||||
"label": "Qty",
|
||||
"name": "${QUANTITY}",
|
||||
"show": true
|
||||
},
|
||||
{
|
||||
"group_by": true,
|
||||
"label": "DNP",
|
||||
"name": "${DNP}",
|
||||
"show": true
|
||||
}
|
||||
],
|
||||
"filter_string": "",
|
||||
"group_symbols": true,
|
||||
"name": "Grouped By Value",
|
||||
"sort_asc": true,
|
||||
"sort_field": "Reference"
|
||||
},
|
||||
"connection_grid_size": 50.0,
|
||||
"drawing": {
|
||||
"dashed_lines_dash_length_ratio": 12.0,
|
||||
"dashed_lines_gap_length_ratio": 3.0,
|
||||
"default_line_thickness": 6.0,
|
||||
"default_text_size": 50.0,
|
||||
"field_names": [],
|
||||
"intersheets_ref_own_page": false,
|
||||
"intersheets_ref_prefix": "",
|
||||
"intersheets_ref_short": false,
|
||||
"intersheets_ref_show": false,
|
||||
"intersheets_ref_suffix": "",
|
||||
"junction_size_choice": 3,
|
||||
"label_size_ratio": 0.375,
|
||||
"operating_point_overlay_i_precision": 3,
|
||||
"operating_point_overlay_i_range": "~A",
|
||||
"operating_point_overlay_v_precision": 3,
|
||||
"operating_point_overlay_v_range": "~V",
|
||||
"overbar_offset_ratio": 1.23,
|
||||
"pin_symbol_size": 25.0,
|
||||
"text_offset_ratio": 0.15
|
||||
},
|
||||
"legacy_lib_dir": "",
|
||||
"legacy_lib_list": [],
|
||||
"meta": {
|
||||
"version": 1
|
||||
},
|
||||
"net_format_name": "",
|
||||
"ngspice": {
|
||||
"fix_include_paths": true,
|
||||
"meta": {
|
||||
"version": 0
|
||||
},
|
||||
"model_mode": 4,
|
||||
"workbook_filename": "a-multi.wbk"
|
||||
},
|
||||
"page_layout_descr_file": "",
|
||||
"plot_directory": "",
|
||||
"spice_current_sheet_as_root": false,
|
||||
"spice_external_command": "spice \"%I\"",
|
||||
"spice_model_current_sheet_as_root": true,
|
||||
"spice_save_all_currents": false,
|
||||
"spice_save_all_dissipations": false,
|
||||
"spice_save_all_voltages": false,
|
||||
"subpart_first_id": 65,
|
||||
"subpart_id_separator": 0
|
||||
},
|
||||
"sheets": [
|
||||
[
|
||||
"e63e39d7-6ac0-4ffd-8aa3-1841a4541b55",
|
||||
"Root"
|
||||
]
|
||||
],
|
||||
"text_variables": {}
|
||||
}
|
||||
LOADING design file
41
demos/simulation/analog-multiplier/a-multi.wbk
Normal file
41
demos/simulation/analog-multiplier/a-multi.wbk
Normal file
@ -0,0 +1,41 @@
|
||||
{
|
||||
"last_sch_text_sim_command": ".tran 1u 10m",
|
||||
"tabs": [
|
||||
{
|
||||
"analysis": "TRAN",
|
||||
"commands": [
|
||||
".tran 1u 10m",
|
||||
".kicad adjustpaths",
|
||||
".save all"
|
||||
],
|
||||
"dottedSecondary": false,
|
||||
"margins": {
|
||||
"bottom": 45,
|
||||
"left": 70,
|
||||
"right": 70,
|
||||
"top": 30
|
||||
},
|
||||
"measurements": [],
|
||||
"showGrid": true,
|
||||
"traces": [
|
||||
{
|
||||
"color": "rgb(228, 26, 28)",
|
||||
"signal": "V(/in1)",
|
||||
"trace_type": 257
|
||||
},
|
||||
{
|
||||
"color": "rgb(55, 126, 184)",
|
||||
"signal": "V(/in2)",
|
||||
"trace_type": 257
|
||||
},
|
||||
{
|
||||
"color": "rgb(77, 175, 74)",
|
||||
"signal": "V(/out)",
|
||||
"trace_type": 257
|
||||
}
|
||||
]
|
||||
}
|
||||
],
|
||||
"user_defined_signals": [],
|
||||
"version": 6
|
||||
}
|
||||
6
demos/simulation/analog-multiplier/mult.lib
Normal file
6
demos/simulation/analog-multiplier/mult.lib
Normal file
@ -0,0 +1,6 @@
|
||||
* multiplier subcircuit
|
||||
.subckt mult in1 in2 out
|
||||
A1 [in1 in2] out mul
|
||||
.model mul mult
|
||||
.ends
|
||||
|
||||
demos/simulation/class-d/AudioDriver.kicad_sym
Normal file
LOADING design file
391
demos/simulation/class-d/Class-D.kicad_pro
Normal file
391
demos/simulation/class-d/Class-D.kicad_pro
Normal file
@ -0,0 +1,391 @@
|
||||
{
|
||||
"board": {
|
||||
"3dviewports": [],
|
||||
"ipc2581": {
|
||||
"dist": "",
|
||||
"distpn": "",
|
||||
"internal_id": "",
|
||||
"mfg": "",
|
||||
"mpn": ""
|
||||
},
|
||||
"layer_presets": [],
|
||||
"viewports": []
|
||||
},
|
||||
"boards": [],
|
||||
"cvpcb": {
|
||||
"equivalence_files": []
|
||||
},
|
||||
"erc": {
|
||||
"erc_exclusions": [],
|
||||
"meta": {
|
||||
"version": 0
|
||||
},
|
||||
"pin_map": [
|
||||
[
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
2
|
||||
],
|
||||
[
|
||||
0,
|
||||
2,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
2,
|
||||
2,
|
||||
2,
|
||||
2
|
||||
],
|
||||
[
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
1,
|
||||
2
|
||||
],
|
||||
[
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
1,
|
||||
1,
|
||||
2,
|
||||
1,
|
||||
1,
|
||||
2
|
||||
],
|
||||
[
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
2
|
||||
],
|
||||
[
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
2
|
||||
],
|
||||
[
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
0,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
2
|
||||
],
|
||||
[
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
2
|
||||
],
|
||||
[
|
||||
0,
|
||||
2,
|
||||
1,
|
||||
2,
|
||||
0,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
2,
|
||||
2,
|
||||
2,
|
||||
2
|
||||
],
|
||||
[
|
||||
0,
|
||||
2,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
2,
|
||||
0,
|
||||
0,
|
||||
2
|
||||
],
|
||||
[
|
||||
0,
|
||||
2,
|
||||
1,
|
||||
1,
|
||||
0,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
2,
|
||||
0,
|
||||
0,
|
||||
2
|
||||
],
|
||||
[
|
||||
2,
|
||||
2,
|
||||
2,
|
||||
2,
|
||||
2,
|
||||
2,
|
||||
2,
|
||||
2,
|
||||
2,
|
||||
2,
|
||||
2,
|
||||
2
|
||||
]
|
||||
],
|
||||
"rule_severities": {
|
||||
"bus_definition_conflict": "error",
|
||||
"bus_entry_needed": "error",
|
||||
"bus_to_bus_conflict": "error",
|
||||
"bus_to_net_conflict": "error",
|
||||
"conflicting_netclasses": "error",
|
||||
"different_unit_footprint": "error",
|
||||
"different_unit_net": "error",
|
||||
"duplicate_reference": "error",
|
||||
"duplicate_sheet_names": "error",
|
||||
"endpoint_off_grid": "warning",
|
||||
"extra_units": "error",
|
||||
"global_label_dangling": "warning",
|
||||
"hier_label_mismatch": "error",
|
||||
"label_dangling": "error",
|
||||
"lib_symbol_issues": "warning",
|
||||
"missing_bidi_pin": "warning",
|
||||
"missing_input_pin": "warning",
|
||||
"missing_power_pin": "error",
|
||||
"missing_unit": "warning",
|
||||
"multiple_net_names": "warning",
|
||||
"net_not_bus_member": "warning",
|
||||
"no_connect_connected": "warning",
|
||||
"no_connect_dangling": "warning",
|
||||
"pin_not_connected": "error",
|
||||
"pin_not_driven": "error",
|
||||
"pin_to_pin": "warning",
|
||||
"power_pin_not_driven": "error",
|
||||
"similar_labels": "warning",
|
||||
"simulation_model_issue": "ignore",
|
||||
"unannotated": "error",
|
||||
"unit_value_mismatch": "error",
|
||||
"unresolved_variable": "error",
|
||||
"wire_dangling": "error"
|
||||
}
|
||||
},
|
||||
"libraries": {
|
||||
"pinned_footprint_libs": [],
|
||||
"pinned_symbol_libs": []
|
||||
},
|
||||
"meta": {
|
||||
"filename": "Class-D.kicad_pro",
|
||||
"version": 1
|
||||
},
|
||||
"net_settings": {
|
||||
"classes": [
|
||||
{
|
||||
"bus_width": 12,
|
||||
"clearance": 0.2,
|
||||
"diff_pair_gap": 0.25,
|
||||
"diff_pair_via_gap": 0.25,
|
||||
"diff_pair_width": 0.2,
|
||||
"line_style": 0,
|
||||
"microvia_diameter": 0.3,
|
||||
"microvia_drill": 0.1,
|
||||
"name": "Default",
|
||||
"pcb_color": "rgba(0, 0, 0, 0.000)",
|
||||
"schematic_color": "rgba(0, 0, 0, 0.000)",
|
||||
"track_width": 0.2,
|
||||
"via_diameter": 0.6,
|
||||
"via_drill": 0.3,
|
||||
"wire_width": 6
|
||||
}
|
||||
],
|
||||
"meta": {
|
||||
"version": 3
|
||||
},
|
||||
"net_colors": null,
|
||||
"netclass_assignments": null,
|
||||
"netclass_patterns": []
|
||||
},
|
||||
"pcbnew": {
|
||||
"last_paths": {
|
||||
"gencad": "",
|
||||
"idf": "",
|
||||
"netlist": "",
|
||||
"plot": "",
|
||||
"pos_files": "",
|
||||
"specctra_dsn": "",
|
||||
"step": "",
|
||||
"svg": "",
|
||||
"vrml": ""
|
||||
},
|
||||
"page_layout_descr_file": ""
|
||||
},
|
||||
"schematic": {
|
||||
"annotate_start_num": 0,
|
||||
"bom_fmt_presets": [],
|
||||
"bom_fmt_settings": {
|
||||
"field_delimiter": ",",
|
||||
"keep_line_breaks": false,
|
||||
"keep_tabs": false,
|
||||
"name": "CSV",
|
||||
"ref_delimiter": ",",
|
||||
"ref_range_delimiter": "",
|
||||
"string_delimiter": "\""
|
||||
},
|
||||
"bom_presets": [],
|
||||
"bom_settings": {
|
||||
"exclude_dnp": false,
|
||||
"fields_ordered": [
|
||||
{
|
||||
"group_by": false,
|
||||
"label": "Reference",
|
||||
"name": "Reference",
|
||||
"show": true
|
||||
},
|
||||
{
|
||||
"group_by": true,
|
||||
"label": "Value",
|
||||
"name": "Value",
|
||||
"show": true
|
||||
},
|
||||
{
|
||||
"group_by": false,
|
||||
"label": "Datasheet",
|
||||
"name": "Datasheet",
|
||||
"show": true
|
||||
},
|
||||
{
|
||||
"group_by": false,
|
||||
"label": "Footprint",
|
||||
"name": "Footprint",
|
||||
"show": true
|
||||
},
|
||||
{
|
||||
"group_by": false,
|
||||
"label": "Qty",
|
||||
"name": "${QUANTITY}",
|
||||
"show": true
|
||||
},
|
||||
{
|
||||
"group_by": true,
|
||||
"label": "DNP",
|
||||
"name": "${DNP}",
|
||||
"show": true
|
||||
}
|
||||
],
|
||||
"filter_string": "",
|
||||
"group_symbols": true,
|
||||
"name": "Grouped By Value",
|
||||
"sort_asc": true,
|
||||
"sort_field": "Referenz"
|
||||
},
|
||||
"connection_grid_size": 50.0,
|
||||
"drawing": {
|
||||
"dashed_lines_dash_length_ratio": 12.0,
|
||||
"dashed_lines_gap_length_ratio": 3.0,
|
||||
"default_line_thickness": 6.0,
|
||||
"default_text_size": 50.0,
|
||||
"field_names": [],
|
||||
"intersheets_ref_own_page": false,
|
||||
"intersheets_ref_prefix": "",
|
||||
"intersheets_ref_short": false,
|
||||
"intersheets_ref_show": false,
|
||||
"intersheets_ref_suffix": "",
|
||||
"junction_size_choice": 3,
|
||||
"label_size_ratio": 0.375,
|
||||
"operating_point_overlay_i_precision": 3,
|
||||
"operating_point_overlay_i_range": "~A",
|
||||
"operating_point_overlay_v_precision": 3,
|
||||
"operating_point_overlay_v_range": "~V",
|
||||
"overbar_offset_ratio": 1.23,
|
||||
"pin_symbol_size": 25.0,
|
||||
"text_offset_ratio": 0.15
|
||||
},
|
||||
"legacy_lib_dir": "",
|
||||
"legacy_lib_list": [],
|
||||
"meta": {
|
||||
"version": 1
|
||||
},
|
||||
"net_format_name": "",
|
||||
"ngspice": {
|
||||
"fix_include_paths": true,
|
||||
"meta": {
|
||||
"version": 0
|
||||
},
|
||||
"model_mode": 4,
|
||||
"workbook_filename": "Class-D.wbk"
|
||||
},
|
||||
"page_layout_descr_file": "",
|
||||
"plot_directory": "",
|
||||
"spice_current_sheet_as_root": false,
|
||||
"spice_external_command": "spice \"%I\"",
|
||||
"spice_model_current_sheet_as_root": true,
|
||||
"spice_save_all_currents": false,
|
||||
"spice_save_all_dissipations": false,
|
||||
"spice_save_all_voltages": false,
|
||||
"subpart_first_id": 65,
|
||||
"subpart_id_separator": 0
|
||||
},
|
||||
"sheets": [
|
||||
[
|
||||
"30d43cb8-f82b-4a5d-811a-ca847a6b3021",
|
||||
"Root"
|
||||
]
|
||||
],
|
||||
"text_variables": {}
|
||||
}
|
||||
demos/simulation/class-d/Class-D.kicad_sch
Normal file
LOADING design file
56
demos/simulation/class-d/Class-D.wbk
Normal file
56
demos/simulation/class-d/Class-D.wbk
Normal file
@ -0,0 +1,56 @@
|
||||
{
|
||||
"last_sch_text_sim_command": "",
|
||||
"tabs": [
|
||||
{
|
||||
"analysis": "TRAN",
|
||||
"commands": [
|
||||
".tran 10n 3m",
|
||||
".kicad adjustpaths",
|
||||
".save all",
|
||||
".probe alli"
|
||||
],
|
||||
"dottedSecondary": true,
|
||||
"margins": {
|
||||
"bottom": 45,
|
||||
"left": 70,
|
||||
"right": 140,
|
||||
"top": 30
|
||||
},
|
||||
"measurements": [
|
||||
{
|
||||
"expr": "RMS P(R15)",
|
||||
"format": "3~W"
|
||||
}
|
||||
],
|
||||
"showGrid": true,
|
||||
"traces": [
|
||||
{
|
||||
"color": "rgb(77, 175, 74)",
|
||||
"cursor1": {
|
||||
"position": 0.008058823529411764,
|
||||
"x_format": "3~s",
|
||||
"y_format": "3~W"
|
||||
},
|
||||
"cursorD": {
|
||||
"x_format": "3~s",
|
||||
"y_format": "3~V"
|
||||
},
|
||||
"signal": "P(R15)",
|
||||
"trace_type": 272
|
||||
},
|
||||
{
|
||||
"color": "rgb(55, 126, 184)",
|
||||
"signal": "V(/Ain)",
|
||||
"trace_type": 257
|
||||
},
|
||||
{
|
||||
"color": "rgb(228, 26, 28)",
|
||||
"signal": "V(/out)",
|
||||
"trace_type": 257
|
||||
}
|
||||
]
|
||||
}
|
||||
],
|
||||
"user_defined_signals": [],
|
||||
"version": 6
|
||||
}
|
||||
55
demos/simulation/class-d/DAudioDriver.lib
Normal file
55
demos/simulation/class-d/DAudioDriver.lib
Normal file
@ -0,0 +1,55 @@
|
||||
* Class D audio amp frontend (to drive a power MOS half bridge)
|
||||
* analog input
|
||||
* pwm clock generator
|
||||
* digital one-shot
|
||||
* non-overlapping clock
|
||||
* two floating half-bridge drivers
|
||||
|
||||
|
||||
* Calling the subcircuit
|
||||
* Xpwm ain lo+ lo- hi+ hi- DAudioDriver freq = 500k dtime = 100n voutp = 1.4 voutn = 0
|
||||
|
||||
.subckt DAudioDriver ain lo+ lo- hi+ hi- params: freq = 317k dtime = 50n voutp = 12 voutn = 0
|
||||
apwm1 ain dfast1 pwm_osc
|
||||
.model pwm_osc d_pwm(cntl_array = [-2 -1.99 1.99 2]
|
||||
+ dc_array = [0.1 0.1 0.9 0.9]
|
||||
+ frequency = {freq} init_phase = 90.0
|
||||
|
||||
a6 dfast1 _d1 inv1
|
||||
.model inv1 d_inverter(rise_delay = 0.3e-9 fall_delay = 0.3e-9
|
||||
+ input_load = 0.5e-12)
|
||||
|
||||
* equalize d1 and _d1
|
||||
abuf2 dfast1 d1 buff2
|
||||
.model buff2 d_buffer(rise_delay = 0.3e-9 fall_delay = 0.3e-9
|
||||
+ input_load = 0.5e-12)
|
||||
|
||||
*** one-shot ***
|
||||
* buffer
|
||||
abuf1 dfast1 d2 buff1
|
||||
.model buff1 d_buffer(rise_delay = {dtime} fall_delay = {dtime}
|
||||
+ input_load = 0.5e-12)
|
||||
* one-shot 1->0 output
|
||||
a9 [dfast1 d2] dos xnor3
|
||||
.model xnor3 d_xnor(rise_delay = 0.2e-9 fall_delay = 0.2e-9
|
||||
+ input_load = 0.5e-12)
|
||||
***
|
||||
|
||||
* outputs: inverted, non-overlapping
|
||||
aand1 [d1 dos] dout1 and1
|
||||
aand2 [_d1 dos] dout2 and1
|
||||
.model and1 d_and(rise_delay = 0.4e-9 fall_delay = 0.4e-9
|
||||
+ input_load = 0.5e-12)
|
||||
|
||||
* analog out, differential
|
||||
abridge1 [dout1] [%vd(lo+ lo-)] dac1
|
||||
abridge2 [dout2] [%vd(hi+ hi-)] dac1
|
||||
.model dac1 dac_bridge(out_low = {voutn} out_high = {voutp} out_undef = 0
|
||||
+ input_load = 5.0e-12 t_rise = 20e-9
|
||||
+ t_fall = 20e-9)
|
||||
|
||||
* test
|
||||
* do we have overlap?
|
||||
* aandtest [dout1 dout2] dtest and1
|
||||
|
||||
.ends
|
||||
89
demos/simulation/class-d/DAudioDriver_os.lib
Normal file
89
demos/simulation/class-d/DAudioDriver_os.lib
Normal file
@ -0,0 +1,89 @@
|
||||
* Class D audio amp frontend (to drive a power MOS half bridge)
|
||||
* analog input
|
||||
* pwm clock generator
|
||||
* digital one-shot
|
||||
* non-overlapping clock
|
||||
* two floating half-bridge drivers
|
||||
|
||||
* Calling the subcircuit model
|
||||
* Xpwm ain lo+ lo- hi+ hi- DAudioDriver freq = 500k dtime = 100n voutp = 1.4 voutn = 0
|
||||
|
||||
* PWM idea with one-shot from
|
||||
* https://www.thequantizer.com/tutorials/dac-and-pwm-kicad-simulation/
|
||||
.subckt pwm_source cntl_in dout params: freq=1.1Meg
|
||||
*****************************************************************
|
||||
* freq = frequency of internal oscillator
|
||||
*****************************************************************
|
||||
ain clk cntl_in 0 out pulse2
|
||||
*****************************************************************
|
||||
* create output by sampeling the control signal every positive
|
||||
* edge of the clk and firing a square with a width determined by the
|
||||
* the controlling input voltage:
|
||||
* vin <= 0.01 then width = 0.01/freq (duty cycle 0.01);
|
||||
* 0.01 < vin < 0.99 then width = vin/freq (duty cycle = vin)
|
||||
* vi >= 0.99 width = 0.99/freq (duty cycle 0.99)
|
||||
*****************************************************************
|
||||
.model pulse2 oneshot(cntl_array = [-2 -1.99 1.99 2]
|
||||
+ pw_array=[{0.01/freq} {0.01/freq} {0.99/freq} {0.99/freq}]
|
||||
+ clk_trig = 0.5 pos_edge_trig = TRUE
|
||||
+ out_low = 0 out_high = 1
|
||||
+ rise_delay = 2.0e-9 fall_delay = 2.0e-9)
|
||||
*****************************************************************
|
||||
* create clock signal
|
||||
*****************************************************************
|
||||
Vclk clk gnd dc 0 pulse(0 1 10n 10n 10n {1/(freq*2)} {1/freq})
|
||||
*****************************************************************
|
||||
* digital output
|
||||
abridge2 [out] [dout] adc_buff
|
||||
.model adc_buff adc_bridge(in_low = 0.5 in_high = 0.5)
|
||||
.ends
|
||||
|
||||
|
||||
.subckt DAudioDriver ain lo+ lo- hi+ hi- params: freq = 317k dtime = 50n voutp = 12 voutn = 0
|
||||
* the intrinsic pwm
|
||||
*apwm1 ain dfast1 pwm_osc
|
||||
*.model pwm_osc d_pwm(cntl_array = [-2 -1.99 1.99 2]
|
||||
*+ dc_array = [0.1 0.1 0.9 0.9]
|
||||
*+ frequency = {freq} init_phase = 90.0
|
||||
|
||||
* the one-shot PWM
|
||||
Xpwm ain dfast1 pwm_source freq={freq}
|
||||
|
||||
a6 dfast1 _d1 inv1
|
||||
.model inv1 d_inverter(rise_delay = 0.3e-9 fall_delay = 0.3e-9
|
||||
+ input_load = 0.5e-12)
|
||||
|
||||
* equalize d1 and _d1
|
||||
abuf2 dfast1 d1 buff2
|
||||
.model buff2 d_buffer(rise_delay = 0.3e-9 fall_delay = 0.3e-9
|
||||
+ input_load = 0.5e-12)
|
||||
|
||||
*** one-shot ***
|
||||
* buffer
|
||||
abuf1 dfast1 d2 buff1
|
||||
.model buff1 d_buffer(rise_delay = {dtime} fall_delay = {dtime}
|
||||
+ input_load = 0.5e-12)
|
||||
* one-shot 1->0 output
|
||||
a9 [dfast1 d2] dos xnor3
|
||||
.model xnor3 d_xnor(rise_delay = 0.2e-9 fall_delay = 0.2e-9
|
||||
+ input_load = 0.5e-12)
|
||||
***
|
||||
|
||||
* outputs: non-inverted and inverted, non-overlapping
|
||||
aand1 [d1 dos] dout1 and1
|
||||
aand2 [_d1 dos] dout2 and1
|
||||
.model and1 d_and(rise_delay = 0.4e-9 fall_delay = 0.4e-9
|
||||
+ input_load = 0.5e-12)
|
||||
|
||||
* analog out, differential
|
||||
abridge1 [dout1] [%vd(lo+ lo-)] dac1
|
||||
abridge2 [dout2] [%vd(hi+ hi-)] dac1
|
||||
.model dac1 dac_bridge(out_low = {voutn} out_high = {voutp} out_undef = 0
|
||||
+ input_load = 5.0e-12 t_rise = 20e-9
|
||||
+ t_fall = 20e-9)
|
||||
|
||||
* test
|
||||
* do we have overlap?
|
||||
* aandtest [dout1 dout2] dtest and1
|
||||
|
||||
.ends
|
||||
4
demos/simulation/class-d/sym-lib-table
Normal file
4
demos/simulation/class-d/sym-lib-table
Normal file
@ -0,0 +1,4 @@
|
||||
(sym_lib_table
|
||||
(version 7)
|
||||
(lib (name "AudioDriver")(type "KiCad")(uri "${KIPRJMOD}/AudioDriver.kicad_sym")(options "")(descr ""))
|
||||
)
|
||||
demos/simulation/gain_control/VCA810.kicad_sym
Normal file
LOADING design file
391
demos/simulation/gain_control/mult_vca810.kicad_pro
Normal file
391
demos/simulation/gain_control/mult_vca810.kicad_pro
Normal file
@ -0,0 +1,391 @@
|
||||
{
|
||||
"board": {
|
||||
"3dviewports": [],
|
||||
"ipc2581": {
|
||||
"dist": "",
|
||||
"distpn": "",
|
||||
"internal_id": "",
|
||||
"mfg": "",
|
||||
"mpn": ""
|
||||
},
|
||||
"layer_presets": [],
|
||||
"viewports": []
|
||||
},
|
||||
"boards": [],
|
||||
"cvpcb": {
|
||||
"equivalence_files": []
|
||||
},
|
||||
"erc": {
|
||||
"erc_exclusions": [],
|
||||
"meta": {
|
||||
"version": 0
|
||||
},
|
||||
"pin_map": [
|
||||
[
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
2
|
||||
],
|
||||
[
|
||||
0,
|
||||
2,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
2,
|
||||
2,
|
||||
2,
|
||||
2
|
||||
],
|
||||
[
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
1,
|
||||
2
|
||||
],
|
||||
[
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
1,
|
||||
1,
|
||||
2,
|
||||
1,
|
||||
1,
|
||||
2
|
||||
],
|
||||
[
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
2
|
||||
],
|
||||
[
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
2
|
||||
],
|
||||
[
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
0,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
2
|
||||
],
|
||||
[
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
2
|
||||
],
|
||||
[
|
||||
0,
|
||||
2,
|
||||
1,
|
||||
2,
|
||||
0,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
2,
|
||||
2,
|
||||
2,
|
||||
2
|
||||
],
|
||||
[
|
||||
0,
|
||||
2,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
2,
|
||||
0,
|
||||
0,
|
||||
2
|
||||
],
|
||||
[
|
||||
0,
|
||||
2,
|
||||
1,
|
||||
1,
|
||||
0,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
2,
|
||||
0,
|
||||
0,
|
||||
2
|
||||
],
|
||||
[
|
||||
2,
|
||||
2,
|
||||
2,
|
||||
2,
|
||||
2,
|
||||
2,
|
||||
2,
|
||||
2,
|
||||
2,
|
||||
2,
|
||||
2,
|
||||
2
|
||||
]
|
||||
],
|
||||
"rule_severities": {
|
||||
"bus_definition_conflict": "error",
|
||||
"bus_entry_needed": "error",
|
||||
"bus_to_bus_conflict": "error",
|
||||
"bus_to_net_conflict": "error",
|
||||
"conflicting_netclasses": "error",
|
||||
"different_unit_footprint": "error",
|
||||
"different_unit_net": "error",
|
||||
"duplicate_reference": "error",
|
||||
"duplicate_sheet_names": "error",
|
||||
"endpoint_off_grid": "warning",
|
||||
"extra_units": "error",
|
||||
"global_label_dangling": "warning",
|
||||
"hier_label_mismatch": "error",
|
||||
"label_dangling": "error",
|
||||
"lib_symbol_issues": "warning",
|
||||
"missing_bidi_pin": "warning",
|
||||
"missing_input_pin": "warning",
|
||||
"missing_power_pin": "error",
|
||||
"missing_unit": "warning",
|
||||
"multiple_net_names": "warning",
|
||||
"net_not_bus_member": "warning",
|
||||
"no_connect_connected": "warning",
|
||||
"no_connect_dangling": "warning",
|
||||
"pin_not_connected": "error",
|
||||
"pin_not_driven": "error",
|
||||
"pin_to_pin": "warning",
|
||||
"power_pin_not_driven": "error",
|
||||
"similar_labels": "warning",
|
||||
"simulation_model_issue": "ignore",
|
||||
"unannotated": "error",
|
||||
"unit_value_mismatch": "error",
|
||||
"unresolved_variable": "error",
|
||||
"wire_dangling": "error"
|
||||
}
|
||||
},
|
||||
"libraries": {
|
||||
"pinned_footprint_libs": [],
|
||||
"pinned_symbol_libs": []
|
||||
},
|
||||
"meta": {
|
||||
"filename": "mult_vca810.kicad_pro",
|
||||
"version": 1
|
||||
},
|
||||
"net_settings": {
|
||||
"classes": [
|
||||
{
|
||||
"bus_width": 12,
|
||||
"clearance": 0.2,
|
||||
"diff_pair_gap": 0.25,
|
||||
"diff_pair_via_gap": 0.25,
|
||||
"diff_pair_width": 0.2,
|
||||
"line_style": 0,
|
||||
"microvia_diameter": 0.3,
|
||||
"microvia_drill": 0.1,
|
||||
"name": "Default",
|
||||
"pcb_color": "rgba(0, 0, 0, 0.000)",
|
||||
"schematic_color": "rgba(0, 0, 0, 0.000)",
|
||||
"track_width": 0.2,
|
||||
"via_diameter": 0.6,
|
||||
"via_drill": 0.3,
|
||||
"wire_width": 6
|
||||
}
|
||||
],
|
||||
"meta": {
|
||||
"version": 3
|
||||
},
|
||||
"net_colors": null,
|
||||
"netclass_assignments": null,
|
||||
"netclass_patterns": []
|
||||
},
|
||||
"pcbnew": {
|
||||
"last_paths": {
|
||||
"gencad": "",
|
||||
"idf": "",
|
||||
"netlist": "",
|
||||
"plot": "",
|
||||
"pos_files": "",
|
||||
"specctra_dsn": "",
|
||||
"step": "",
|
||||
"svg": "",
|
||||
"vrml": ""
|
||||
},
|
||||
"page_layout_descr_file": ""
|
||||
},
|
||||
"schematic": {
|
||||
"annotate_start_num": 0,
|
||||
"bom_fmt_presets": [],
|
||||
"bom_fmt_settings": {
|
||||
"field_delimiter": ",",
|
||||
"keep_line_breaks": false,
|
||||
"keep_tabs": false,
|
||||
"name": "CSV",
|
||||
"ref_delimiter": ",",
|
||||
"ref_range_delimiter": "",
|
||||
"string_delimiter": "\""
|
||||
},
|
||||
"bom_presets": [],
|
||||
"bom_settings": {
|
||||
"exclude_dnp": false,
|
||||
"fields_ordered": [
|
||||
{
|
||||
"group_by": false,
|
||||
"label": "Reference",
|
||||
"name": "Reference",
|
||||
"show": true
|
||||
},
|
||||
{
|
||||
"group_by": true,
|
||||
"label": "Value",
|
||||
"name": "Value",
|
||||
"show": true
|
||||
},
|
||||
{
|
||||
"group_by": false,
|
||||
"label": "Datasheet",
|
||||
"name": "Datasheet",
|
||||
"show": true
|
||||
},
|
||||
{
|
||||
"group_by": false,
|
||||
"label": "Footprint",
|
||||
"name": "Footprint",
|
||||
"show": true
|
||||
},
|
||||
{
|
||||
"group_by": false,
|
||||
"label": "Qty",
|
||||
"name": "${QUANTITY}",
|
||||
"show": true
|
||||
},
|
||||
{
|
||||
"group_by": true,
|
||||
"label": "DNP",
|
||||
"name": "${DNP}",
|
||||
"show": true
|
||||
}
|
||||
],
|
||||
"filter_string": "",
|
||||
"group_symbols": true,
|
||||
"name": "Grouped By Value",
|
||||
"sort_asc": true,
|
||||
"sort_field": "Reference"
|
||||
},
|
||||
"connection_grid_size": 50.0,
|
||||
"drawing": {
|
||||
"dashed_lines_dash_length_ratio": 12.0,
|
||||
"dashed_lines_gap_length_ratio": 3.0,
|
||||
"default_line_thickness": 6.0,
|
||||
"default_text_size": 50.0,
|
||||
"field_names": [],
|
||||
"intersheets_ref_own_page": false,
|
||||
"intersheets_ref_prefix": "",
|
||||
"intersheets_ref_short": false,
|
||||
"intersheets_ref_show": false,
|
||||
"intersheets_ref_suffix": "",
|
||||
"junction_size_choice": 3,
|
||||
"label_size_ratio": 0.375,
|
||||
"operating_point_overlay_i_precision": 3,
|
||||
"operating_point_overlay_i_range": "~A",
|
||||
"operating_point_overlay_v_precision": 3,
|
||||
"operating_point_overlay_v_range": "~V",
|
||||
"overbar_offset_ratio": 1.23,
|
||||
"pin_symbol_size": 25.0,
|
||||
"text_offset_ratio": 0.15
|
||||
},
|
||||
"legacy_lib_dir": "",
|
||||
"legacy_lib_list": [],
|
||||
"meta": {
|
||||
"version": 1
|
||||
},
|
||||
"net_format_name": "",
|
||||
"ngspice": {
|
||||
"fix_include_paths": true,
|
||||
"meta": {
|
||||
"version": 0
|
||||
},
|
||||
"model_mode": 4,
|
||||
"workbook_filename": "mult_vca810.wbk"
|
||||
},
|
||||
"page_layout_descr_file": "",
|
||||
"plot_directory": "",
|
||||
"spice_current_sheet_as_root": false,
|
||||
"spice_external_command": "spice \"%I\"",
|
||||
"spice_model_current_sheet_as_root": true,
|
||||
"spice_save_all_currents": false,
|
||||
"spice_save_all_dissipations": false,
|
||||
"spice_save_all_voltages": false,
|
||||
"subpart_first_id": 65,
|
||||
"subpart_id_separator": 0
|
||||
},
|
||||
"sheets": [
|
||||
[
|
||||
"62c66358-895a-4557-9af0-9d199226cdcd",
|
||||
""
|
||||
]
|
||||
],
|
||||
"text_variables": {}
|
||||
}
|
||||
LOADING design file
45
demos/simulation/gain_control/mult_vca810.wbk
Normal file
45
demos/simulation/gain_control/mult_vca810.wbk
Normal file
@ -0,0 +1,45 @@
|
||||
{
|
||||
"last_sch_text_sim_command": "",
|
||||
"tabs": [
|
||||
{
|
||||
"analysis": "TRAN",
|
||||
"commands": [
|
||||
".tran 10u 30m",
|
||||
".kicad adjustpaths",
|
||||
".save all"
|
||||
],
|
||||
"dottedSecondary": true,
|
||||
"legend": {
|
||||
"x": 101,
|
||||
"y": 34
|
||||
},
|
||||
"margins": {
|
||||
"bottom": 45,
|
||||
"left": 70,
|
||||
"right": 70,
|
||||
"top": 30
|
||||
},
|
||||
"measurements": [],
|
||||
"showGrid": true,
|
||||
"traces": [
|
||||
{
|
||||
"color": "rgb(77, 175, 74)",
|
||||
"signal": "V(/gain)",
|
||||
"trace_type": 257
|
||||
},
|
||||
{
|
||||
"color": "rgb(55, 126, 184)",
|
||||
"signal": "V(/in)",
|
||||
"trace_type": 257
|
||||
},
|
||||
{
|
||||
"color": "rgb(228, 26, 28)",
|
||||
"signal": "V(/out)",
|
||||
"trace_type": 257
|
||||
}
|
||||
]
|
||||
}
|
||||
],
|
||||
"user_defined_signals": [],
|
||||
"version": 6
|
||||
}
|
||||
4
demos/simulation/gain_control/sym-lib-table
Normal file
4
demos/simulation/gain_control/sym-lib-table
Normal file
@ -0,0 +1,4 @@
|
||||
(sym_lib_table
|
||||
(version 7)
|
||||
(lib (name "VCA810")(type "KiCad")(uri "${KIPRJMOD}/VCA810.kicad_sym")(options "")(descr ""))
|
||||
)
|
||||
110
demos/simulation/gain_control/vca810.lib
Normal file
110
demos/simulation/gain_control/vca810.lib
Normal file
@ -0,0 +1,110 @@
|
||||
* VCA810
|
||||
*****************************************************************************
|
||||
* (C) Copyright 2012 Texas Instruments Incorporated. All rights reserved.
|
||||
*****************************************************************************
|
||||
** This model is designed as an aid for customers of Texas Instruments.
|
||||
** TI and its licensors and suppliers make no warranties, either expressed
|
||||
** or implied, with respect to this model, including the warranties of
|
||||
** merchantability or fitness for a particular purpose. The model is
|
||||
** provided solely on an "as is" basis. The entire risk as to its quality
|
||||
** and performance is with the customer.
|
||||
*****************************************************************************
|
||||
*
|
||||
** Released by: WEBENCH(R) Design Center, Texas Instruments Inc.
|
||||
* Part: VCA810
|
||||
* Date: 01/15/2014
|
||||
* Model Type: All In One
|
||||
* Simulator: TINA-TI
|
||||
* Simulator Version: 9.3.80.256 SF-TI
|
||||
* EVM Order Number: N/A
|
||||
* EVM Users Guide: N/A
|
||||
* Datasheet: SBOS275F –JUNE 2003–REVISED DECEMBER 2010
|
||||
*
|
||||
* Model Version: 1.0
|
||||
*
|
||||
*****************************************************************************
|
||||
*
|
||||
* Updates:
|
||||
*
|
||||
* Version 1.0 : Based on Pspice macro netlist w/following comments:
|
||||
* "VCA810 VOLTAGE CONTROLLED AMPLIFIER "MACROMODEL" SUBCIRCUIT
|
||||
* CREATED 7/30/04 RRS"
|
||||
* Release to Web
|
||||
*
|
||||
*****************************************************************************
|
||||
* Notes:
|
||||
* 1. The model still missing dc and noise to be added latter
|
||||
*****************************************************************************
|
||||
*
|
||||
* CONNECTIONS: NON-INVERTING INPUT
|
||||
* | GROUND
|
||||
* | | GAIN CONTROL, VC
|
||||
* | | | OUTPUT
|
||||
* | | | | POSITIVE SUPPLY VOLTAGE
|
||||
* | | | | | NEGATIVE SUPPLY VOLTAGE
|
||||
* | | | | | | INVERTING INPUT
|
||||
* | | | | | | |
|
||||
.SUBCKT VCA810 1 2 3 5 6 7 8
|
||||
* CONTROL VOLTAGE
|
||||
Q1 7 3 13 P
|
||||
C1 3 7 1E-12
|
||||
Q2 7 2 13 P
|
||||
I1 6 13 384E-6
|
||||
Q3 10 11 7 N
|
||||
R2 6 10 2
|
||||
E1 11 7 POLY(1) (3,0) 0.45 -0.11911
|
||||
G3 12 0 POLY(1) (10,6) 0 1
|
||||
R3 12 0 139
|
||||
C3 12 0 1.145E-9
|
||||
G1 6 7 POLY(1) (6,10) 13.5102E-3 -0.489
|
||||
G2 0 7 POLY(1) (6,10) 1.7958E-3 2.939E-3
|
||||
* INPUT STAGE
|
||||
Q01 20 1 26 N
|
||||
C01 1 0 1E-12
|
||||
Q02 21 8 26 N
|
||||
C02 8 0 1E-12
|
||||
R01 20 27 1E3
|
||||
D01 29 27 DX
|
||||
D03 6 29 DX
|
||||
R02 21 28 1E3
|
||||
D02 24 28 DX
|
||||
D04 6 24 DX
|
||||
IS 26 7 2.32E-3
|
||||
* GAIN STAGE 1
|
||||
R31 31 0 1E6
|
||||
G31 31 0 POLY(2) (8,1) (12,0) 0 0 0 0 1.1E-6 0
|
||||
* GAIN STAGE 2
|
||||
R41 41 44 20E3
|
||||
C41 41 44 230.25E-15
|
||||
G41 41 44 0 31 1E-3
|
||||
D41 41 43 DX
|
||||
E41 44 43 POLY(1) (3,0) 100.2 14.87
|
||||
R42 41 45 20E3
|
||||
C42 41 45 230.25E-15
|
||||
G42 41 45 0 31 1E-3
|
||||
D42 42 41 DX
|
||||
E42 42 45 POLY(1) (3,0) 100.2 14.87
|
||||
E43 44 0 6 0 20
|
||||
E44 0 45 0 7 20
|
||||
* OUTPUT STAGE
|
||||
E51 55 0 41 0 50E-3
|
||||
D53 55 51 DX
|
||||
D54 52 55 DX
|
||||
D55 6 53 DX
|
||||
D56 6 54 DX
|
||||
D57 7 53 DZ
|
||||
D58 7 54 DZ
|
||||
G54 53 7 5 55 50E-3
|
||||
G53 54 7 55 5 50E-3
|
||||
V53 51 5 0.1833
|
||||
V54 5 52 0.1833
|
||||
G51 5 6 6 55 50E-3
|
||||
G52 7 5 55 7 50E-3
|
||||
R53 6 5 20
|
||||
R54 7 5 20
|
||||
.MODEL N NPN (IS=1E-12 BF=193)
|
||||
.MODEL P PNP (IS=1E-12 BF=96)
|
||||
.MODEL DX D(IS=1E-15 BV=200)
|
||||
.MODEL DZ D(IS=1E-15 BV=50)
|
||||
.ENDS
|
||||
*$
|
||||
391
demos/simulation/generic_models/generic_opamp_bip.kicad_pro
Normal file
391
demos/simulation/generic_models/generic_opamp_bip.kicad_pro
Normal file
@ -0,0 +1,391 @@
|
||||
{
|
||||
"board": {
|
||||
"3dviewports": [],
|
||||
"ipc2581": {
|
||||
"dist": "",
|
||||
"distpn": "",
|
||||
"internal_id": "",
|
||||
"mfg": "",
|
||||
"mpn": ""
|
||||
},
|
||||
"layer_presets": [],
|
||||
"viewports": []
|
||||
},
|
||||
"boards": [],
|
||||
"cvpcb": {
|
||||
"equivalence_files": []
|
||||
},
|
||||
"erc": {
|
||||
"erc_exclusions": [],
|
||||
"meta": {
|
||||
"version": 0
|
||||
},
|
||||
"pin_map": [
|
||||
[
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
2
|
||||
],
|
||||
[
|
||||
0,
|
||||
2,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
2,
|
||||
2,
|
||||
2,
|
||||
2
|
||||
],
|
||||
[
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
1,
|
||||
2
|
||||
],
|
||||
[
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
1,
|
||||
1,
|
||||
2,
|
||||
1,
|
||||
1,
|
||||
2
|
||||
],
|
||||
[
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
2
|
||||
],
|
||||
[
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
2
|
||||
],
|
||||
[
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
0,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
2
|
||||
],
|
||||
[
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
2
|
||||
],
|
||||
[
|
||||
0,
|
||||
2,
|
||||
1,
|
||||
2,
|
||||
0,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
2,
|
||||
2,
|
||||
2,
|
||||
2
|
||||
],
|
||||
[
|
||||
0,
|
||||
2,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
2,
|
||||
0,
|
||||
0,
|
||||
2
|
||||
],
|
||||
[
|
||||
0,
|
||||
2,
|
||||
1,
|
||||
1,
|
||||
0,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
2,
|
||||
0,
|
||||
0,
|
||||
2
|
||||
],
|
||||
[
|
||||
2,
|
||||
2,
|
||||
2,
|
||||
2,
|
||||
2,
|
||||
2,
|
||||
2,
|
||||
2,
|
||||
2,
|
||||
2,
|
||||
2,
|
||||
2
|
||||
]
|
||||
],
|
||||
"rule_severities": {
|
||||
"bus_definition_conflict": "error",
|
||||
"bus_entry_needed": "error",
|
||||
"bus_to_bus_conflict": "error",
|
||||
"bus_to_net_conflict": "error",
|
||||
"conflicting_netclasses": "error",
|
||||
"different_unit_footprint": "error",
|
||||
"different_unit_net": "error",
|
||||
"duplicate_reference": "error",
|
||||
"duplicate_sheet_names": "error",
|
||||
"endpoint_off_grid": "warning",
|
||||
"extra_units": "error",
|
||||
"global_label_dangling": "warning",
|
||||
"hier_label_mismatch": "error",
|
||||
"label_dangling": "error",
|
||||
"lib_symbol_issues": "warning",
|
||||
"missing_bidi_pin": "warning",
|
||||
"missing_input_pin": "warning",
|
||||
"missing_power_pin": "error",
|
||||
"missing_unit": "warning",
|
||||
"multiple_net_names": "warning",
|
||||
"net_not_bus_member": "warning",
|
||||
"no_connect_connected": "warning",
|
||||
"no_connect_dangling": "warning",
|
||||
"pin_not_connected": "error",
|
||||
"pin_not_driven": "error",
|
||||
"pin_to_pin": "warning",
|
||||
"power_pin_not_driven": "error",
|
||||
"similar_labels": "warning",
|
||||
"simulation_model_issue": "ignore",
|
||||
"unannotated": "error",
|
||||
"unit_value_mismatch": "error",
|
||||
"unresolved_variable": "error",
|
||||
"wire_dangling": "error"
|
||||
}
|
||||
},
|
||||
"libraries": {
|
||||
"pinned_footprint_libs": [],
|
||||
"pinned_symbol_libs": []
|
||||
},
|
||||
"meta": {
|
||||
"filename": "generic_opamp_bip.kicad_pro",
|
||||
"version": 1
|
||||
},
|
||||
"net_settings": {
|
||||
"classes": [
|
||||
{
|
||||
"bus_width": 12,
|
||||
"clearance": 0.2,
|
||||
"diff_pair_gap": 0.25,
|
||||
"diff_pair_via_gap": 0.25,
|
||||
"diff_pair_width": 0.2,
|
||||
"line_style": 0,
|
||||
"microvia_diameter": 0.3,
|
||||
"microvia_drill": 0.1,
|
||||
"name": "Default",
|
||||
"pcb_color": "rgba(0, 0, 0, 0.000)",
|
||||
"schematic_color": "rgba(0, 0, 0, 0.000)",
|
||||
"track_width": 0.2,
|
||||
"via_diameter": 0.6,
|
||||
"via_drill": 0.3,
|
||||
"wire_width": 6
|
||||
}
|
||||
],
|
||||
"meta": {
|
||||
"version": 3
|
||||
},
|
||||
"net_colors": null,
|
||||
"netclass_assignments": null,
|
||||
"netclass_patterns": []
|
||||
},
|
||||
"pcbnew": {
|
||||
"last_paths": {
|
||||
"gencad": "",
|
||||
"idf": "",
|
||||
"netlist": "",
|
||||
"plot": "",
|
||||
"pos_files": "",
|
||||
"specctra_dsn": "",
|
||||
"step": "",
|
||||
"svg": "",
|
||||
"vrml": ""
|
||||
},
|
||||
"page_layout_descr_file": ""
|
||||
},
|
||||
"schematic": {
|
||||
"annotate_start_num": 0,
|
||||
"bom_fmt_presets": [],
|
||||
"bom_fmt_settings": {
|
||||
"field_delimiter": ",",
|
||||
"keep_line_breaks": false,
|
||||
"keep_tabs": false,
|
||||
"name": "CSV",
|
||||
"ref_delimiter": ",",
|
||||
"ref_range_delimiter": "",
|
||||
"string_delimiter": "\""
|
||||
},
|
||||
"bom_presets": [],
|
||||
"bom_settings": {
|
||||
"exclude_dnp": false,
|
||||
"fields_ordered": [
|
||||
{
|
||||
"group_by": false,
|
||||
"label": "Reference",
|
||||
"name": "Reference",
|
||||
"show": true
|
||||
},
|
||||
{
|
||||
"group_by": true,
|
||||
"label": "Value",
|
||||
"name": "Value",
|
||||
"show": true
|
||||
},
|
||||
{
|
||||
"group_by": false,
|
||||
"label": "Datasheet",
|
||||
"name": "Datasheet",
|
||||
"show": true
|
||||
},
|
||||
{
|
||||
"group_by": false,
|
||||
"label": "Footprint",
|
||||
"name": "Footprint",
|
||||
"show": true
|
||||
},
|
||||
{
|
||||
"group_by": false,
|
||||
"label": "Qty",
|
||||
"name": "${QUANTITY}",
|
||||
"show": true
|
||||
},
|
||||
{
|
||||
"group_by": true,
|
||||
"label": "DNP",
|
||||
"name": "${DNP}",
|
||||
"show": true
|
||||
}
|
||||
],
|
||||
"filter_string": "",
|
||||
"group_symbols": true,
|
||||
"name": "Grouped By Value",
|
||||
"sort_asc": true,
|
||||
"sort_field": "Reference"
|
||||
},
|
||||
"connection_grid_size": 50.0,
|
||||
"drawing": {
|
||||
"dashed_lines_dash_length_ratio": 12.0,
|
||||
"dashed_lines_gap_length_ratio": 3.0,
|
||||
"default_line_thickness": 6.0,
|
||||
"default_text_size": 50.0,
|
||||
"field_names": [],
|
||||
"intersheets_ref_own_page": false,
|
||||
"intersheets_ref_prefix": "",
|
||||
"intersheets_ref_short": false,
|
||||
"intersheets_ref_show": false,
|
||||
"intersheets_ref_suffix": "",
|
||||
"junction_size_choice": 3,
|
||||
"label_size_ratio": 0.375,
|
||||
"operating_point_overlay_i_precision": 3,
|
||||
"operating_point_overlay_i_range": "~A",
|
||||
"operating_point_overlay_v_precision": 3,
|
||||
"operating_point_overlay_v_range": "~V",
|
||||
"overbar_offset_ratio": 1.23,
|
||||
"pin_symbol_size": 25.0,
|
||||
"text_offset_ratio": 0.15
|
||||
},
|
||||
"legacy_lib_dir": "",
|
||||
"legacy_lib_list": [],
|
||||
"meta": {
|
||||
"version": 1
|
||||
},
|
||||
"net_format_name": "",
|
||||
"ngspice": {
|
||||
"fix_include_paths": true,
|
||||
"meta": {
|
||||
"version": 0
|
||||
},
|
||||
"model_mode": 4,
|
||||
"workbook_filename": "generic_opamp_bip.wbk"
|
||||
},
|
||||
"page_layout_descr_file": "",
|
||||
"plot_directory": "",
|
||||
"spice_current_sheet_as_root": false,
|
||||
"spice_external_command": "spice \"%I\"",
|
||||
"spice_model_current_sheet_as_root": true,
|
||||
"spice_save_all_currents": false,
|
||||
"spice_save_all_dissipations": false,
|
||||
"spice_save_all_voltages": false,
|
||||
"subpart_first_id": 65,
|
||||
"subpart_id_separator": 0
|
||||
},
|
||||
"sheets": [
|
||||
[
|
||||
"7e4dfe8a-5df9-4426-b328-4b07a6aa7235",
|
||||
"Root"
|
||||
]
|
||||
],
|
||||
"text_variables": {}
|
||||
}
|
||||
@ -0,0 +1 @@
|
||||
.model 1N4002 D (Is=14.11n N=1.984 Rs=33.89E-3 Ikf=94.81 Xti=3 Eg=1.110 Cjo=51.17E-12 M=.2762 Vj=.3905 Fc=.5 Isr=100.0E-12 Nr=2 Bv=100.1 Ibv=10 Tt=4.761E-6)
|
||||
69
demos/simulation/power_supplies/LM317_power_supply/LM317.lib
Normal file
69
demos/simulation/power_supplies/LM317_power_supply/LM317.lib
Normal file
@ -0,0 +1,69 @@
|
||||
.SUBCKT LM317 IN ADJ OUT_0
|
||||
R_R1 VXX IN {RINP}
|
||||
R_R6 N242982 VYY 10 TC=0,0
|
||||
R_R5 VZZ VYY {ROUT}
|
||||
E_ABM1 N242982 0 VALUE { MIN(V(VXX), (V(Vzz)+(ILIM*ROUT))) }
|
||||
R_R2 N222524 VXX {PSRR*RINP}
|
||||
R_U1_R2 0 U1_N26728 1G
|
||||
E_U1_ABM5 U1_N31197 0 VALUE { MIN(V(U1_N26728),
|
||||
+ MAX(V(IN) - {DROP}, 0)) }
|
||||
C_U1_C2 0 U1_N26728 1n
|
||||
R_U1_R1 0 U1_N08257 1G
|
||||
R_U1_R4 U1_N28933 U1_N26728 10 TC=0,0
|
||||
R_U1_R5 U1_N31197 N222524 10 TC=0,0
|
||||
C_U1_C3 0 N222524 1n
|
||||
X_U1_U2 IN U1_N12783 U1_N12664 U1_UVLO_OK COMPHYS_BASIC_GEN PARAMS:
|
||||
+ VDD=1 VSS=0 VTHRESH=0.5
|
||||
C_U1_C1 0 U1_N08257 {1e-6*SQRT(TTRN)}
|
||||
V_U1_V4 U1_N12783 0 {UVLO}
|
||||
V_U1_V3 U1_N12664 0 {UHYS}
|
||||
E_U1_ABM6 U1_EN_OUT 0 VALUE { IF(V(U1_UVLO_OK)> 0.6, {VREF}, 0) }
|
||||
R_U1_R3 U1_EN_OUT U1_N08257 {3.333e5*SQRT(TTRN)} TC=0,0
|
||||
E_U1_ABM4 U1_N28933 0 VALUE { V(U1_N08257)*
|
||||
+ (ABS(V(OUT_0))/(ABS(V(OUT_0)-v(ADJ)))) }
|
||||
X_U2 0 OUT_0 d_d PARAMS:
|
||||
X_F1 VZZ OUT_0 IN VYY LM317_TRANS_F1
|
||||
C_C1 VXX IN {1/(6.28*RINP*POLE)}
|
||||
C_C2 VXX N222524 {1/(6.28*PSRR*RINP*ZERO)}
|
||||
C_C3 0 VYY 1n
|
||||
.PARAM psrr=7.9432e-4 uvlo=0 ilim=2.2 pole=15k rinp=1e7 zero=100e6 rout=0.4m
|
||||
+ ttrn=1e-4 vref=1.25 uhys=0 drop=.5
|
||||
.ENDS LM317_TRANS
|
||||
*$
|
||||
.SUBCKT LM317_TRANS_F1 1 2 3 4
|
||||
F_F1 3 4 VF_F1 1
|
||||
VF_F1 1 2 0V
|
||||
.ENDS LM317_TRANS_F1
|
||||
*$
|
||||
.SUBCKT COMP_BASIC_GEN INP INM Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5
|
||||
E_ABM Yint 0 VALUE {IF (V(INP) >
|
||||
+ V(INM), {VDD},{VSS})}
|
||||
R1 Yint Y 1
|
||||
C1 Y 0 1n
|
||||
.ENDS COMP_BASIC_GEN
|
||||
*$
|
||||
.SUBCKT COMPHYS_BASIC_GEN INP INM HYS OUT PARAMS: VDD=1 VSS=0 VTHRESH=0.5
|
||||
EIN INP1 INM1 INP INM 1
|
||||
EHYS INP1 INP2 VALUE { IF( V(1) > {VTHRESH},-V(HYS),0) }
|
||||
EOUT OUT 0 VALUE { IF( V(INP2)>V(INM1), {VDD} ,{VSS}) }
|
||||
R1 OUT 1 1
|
||||
C1 1 0 5n
|
||||
RINP1 INP1 0 1K
|
||||
.ENDS COMPHYS_BASIC_GEN
|
||||
*$
|
||||
.SUBCKT COMPHYS2_BASIC_GEN INP INM HYS OUT PARAMS: VDD=1 VSS=0 VTHRESH=0.5
|
||||
+ T=10
|
||||
EIN INP1 INM1 INP INM 1
|
||||
EHYS INM2 INM1 VALUE { IF( V(1) > {VTHRESH},-V(HYS)/2,V(HYS)/2) }
|
||||
EOUT OUT 0 VALUE { IF( V(INP1)>V(INM2), {VDD} ,{VSS}) }
|
||||
R1 OUT 1 1
|
||||
C1 1 0 {T*1e-9}
|
||||
RINP1 INP1 0 10K
|
||||
RINM2 INM2 0 10K
|
||||
.ENDS COMPHYS2_BASIC_GEN
|
||||
*$
|
||||
.SUBCKT D_D 1 2
|
||||
D1 1 2 DD
|
||||
.MODEL DD D (IS=1E-015 N=0.01 TT=1e-011)
|
||||
.ENDS D_D
|
||||
*$
|
||||
@ -0,0 +1,7 @@
|
||||
.subckt D_Bridge_+-AA 1 2 3 4
|
||||
D1 3 1 1N4001
|
||||
D2 4 1 1N4001
|
||||
D3 2 3 1N4001
|
||||
D4 2 4 1N4001
|
||||
.MODEL 1N4001 D(IS=2.55E-9 RS=0.042 N=1.75 TT=5.76E-6 CJO=1.85E-11 VJ=0.75 M=0.333 BV=50 IBV=1E-5)
|
||||
.ends D_Bridge_+-AA
|
||||
@ -0,0 +1,416 @@
|
||||
{
|
||||
"board": {
|
||||
"3dviewports": [],
|
||||
"design_settings": {
|
||||
"defaults": {
|
||||
"board_outline_line_width": 0.1,
|
||||
"copper_line_width": 0.2,
|
||||
"copper_text_size_h": 1.5,
|
||||
"copper_text_size_v": 1.5,
|
||||
"copper_text_thickness": 0.3,
|
||||
"other_line_width": 0.15,
|
||||
"silk_line_width": 0.15,
|
||||
"silk_text_size_h": 1.0,
|
||||
"silk_text_size_v": 1.0,
|
||||
"silk_text_thickness": 0.15
|
||||
},
|
||||
"diff_pair_dimensions": [],
|
||||
"drc_exclusions": [],
|
||||
"rules": {
|
||||
"solder_mask_clearance": 0.0,
|
||||
"solder_mask_min_width": 0.0
|
||||
},
|
||||
"track_widths": [],
|
||||
"via_dimensions": []
|
||||
},
|
||||
"ipc2581": {
|
||||
"dist": "",
|
||||
"distpn": "",
|
||||
"internal_id": "",
|
||||
"mfg": "",
|
||||
"mpn": ""
|
||||
},
|
||||
"layer_presets": [],
|
||||
"viewports": []
|
||||
},
|
||||
"boards": [],
|
||||
"cvpcb": {
|
||||
"equivalence_files": []
|
||||
},
|
||||
"erc": {
|
||||
"erc_exclusions": [],
|
||||
"meta": {
|
||||
"version": 0
|
||||
},
|
||||
"pin_map": [
|
||||
[
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
2
|
||||
],
|
||||
[
|
||||
0,
|
||||
2,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
2,
|
||||
2,
|
||||
2,
|
||||
2
|
||||
],
|
||||
[
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
1,
|
||||
2
|
||||
],
|
||||
[
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
1,
|
||||
1,
|
||||
2,
|
||||
1,
|
||||
1,
|
||||
2
|
||||
],
|
||||
[
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
2
|
||||
],
|
||||
[
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
2
|
||||
],
|
||||
[
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
0,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
2
|
||||
],
|
||||
[
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
2
|
||||
],
|
||||
[
|
||||
0,
|
||||
2,
|
||||
1,
|
||||
2,
|
||||
0,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
2,
|
||||
2,
|
||||
2,
|
||||
2
|
||||
],
|
||||
[
|
||||
0,
|
||||
2,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
2,
|
||||
0,
|
||||
0,
|
||||
2
|
||||
],
|
||||
[
|
||||
0,
|
||||
2,
|
||||
1,
|
||||
1,
|
||||
0,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
2,
|
||||
0,
|
||||
0,
|
||||
2
|
||||
],
|
||||
[
|
||||
2,
|
||||
2,
|
||||
2,
|
||||
2,
|
||||
2,
|
||||
2,
|
||||
2,
|
||||
2,
|
||||
2,
|
||||
2,
|
||||
2,
|
||||
2
|
||||
]
|
||||
],
|
||||
"rule_severities": {
|
||||
"bus_definition_conflict": "error",
|
||||
"bus_entry_needed": "error",
|
||||
"bus_label_syntax": "error",
|
||||
"bus_to_bus_conflict": "error",
|
||||
"bus_to_net_conflict": "error",
|
||||
"conflicting_netclasses": "error",
|
||||
"different_unit_footprint": "error",
|
||||
"different_unit_net": "error",
|
||||
"duplicate_reference": "error",
|
||||
"duplicate_sheet_names": "error",
|
||||
"endpoint_off_grid": "warning",
|
||||
"extra_units": "error",
|
||||
"global_label_dangling": "warning",
|
||||
"hier_label_mismatch": "error",
|
||||
"label_dangling": "error",
|
||||
"lib_symbol_issues": "warning",
|
||||
"missing_bidi_pin": "warning",
|
||||
"missing_input_pin": "warning",
|
||||
"missing_power_pin": "error",
|
||||
"missing_unit": "warning",
|
||||
"multiple_net_names": "warning",
|
||||
"net_not_bus_member": "warning",
|
||||
"no_connect_connected": "warning",
|
||||
"no_connect_dangling": "warning",
|
||||
"pin_not_connected": "error",
|
||||
"pin_not_driven": "error",
|
||||
"pin_to_pin": "warning",
|
||||
"power_pin_not_driven": "error",
|
||||
"similar_labels": "warning",
|
||||
"simulation_model_issue": "ignore",
|
||||
"unannotated": "error",
|
||||
"unit_value_mismatch": "error",
|
||||
"unresolved_variable": "error",
|
||||
"wire_dangling": "error"
|
||||
}
|
||||
},
|
||||
"libraries": {
|
||||
"pinned_footprint_libs": [],
|
||||
"pinned_symbol_libs": []
|
||||
},
|
||||
"meta": {
|
||||
"filename": "power_supply.kicad_pro",
|
||||
"version": 1
|
||||
},
|
||||
"net_settings": {
|
||||
"classes": [
|
||||
{
|
||||
"bus_width": 12,
|
||||
"clearance": 0.2,
|
||||
"diff_pair_gap": 0.25,
|
||||
"diff_pair_via_gap": 0.25,
|
||||
"diff_pair_width": 0.2,
|
||||
"line_style": 0,
|
||||
"microvia_diameter": 0.3,
|
||||
"microvia_drill": 0.1,
|
||||
"name": "Default",
|
||||
"pcb_color": "rgba(0, 0, 0, 0.000)",
|
||||
"schematic_color": "rgba(0, 0, 0, 0.000)",
|
||||
"track_width": 0.25,
|
||||
"via_diameter": 0.8,
|
||||
"via_drill": 0.4,
|
||||
"wire_width": 6
|
||||
}
|
||||
],
|
||||
"meta": {
|
||||
"version": 3
|
||||
},
|
||||
"net_colors": null,
|
||||
"netclass_assignments": null,
|
||||
"netclass_patterns": []
|
||||
},
|
||||
"pcbnew": {
|
||||
"last_paths": {
|
||||
"gencad": "",
|
||||
"idf": "",
|
||||
"netlist": "",
|
||||
"plot": "",
|
||||
"pos_files": "",
|
||||
"specctra_dsn": "",
|
||||
"step": "",
|
||||
"svg": "",
|
||||
"vrml": ""
|
||||
},
|
||||
"page_layout_descr_file": ""
|
||||
},
|
||||
"schematic": {
|
||||
"annotate_start_num": 0,
|
||||
"bom_fmt_presets": [],
|
||||
"bom_fmt_settings": {
|
||||
"field_delimiter": ",",
|
||||
"keep_line_breaks": false,
|
||||
"keep_tabs": false,
|
||||
"name": "CSV",
|
||||
"ref_delimiter": ",",
|
||||
"ref_range_delimiter": "",
|
||||
"string_delimiter": "\""
|
||||
},
|
||||
"bom_presets": [],
|
||||
"bom_settings": {
|
||||
"exclude_dnp": false,
|
||||
"fields_ordered": [
|
||||
{
|
||||
"group_by": false,
|
||||
"label": "Reference",
|
||||
"name": "Reference",
|
||||
"show": true
|
||||
},
|
||||
{
|
||||
"group_by": true,
|
||||
"label": "Value",
|
||||
"name": "Value",
|
||||
"show": true
|
||||
},
|
||||
{
|
||||
"group_by": false,
|
||||
"label": "Datasheet",
|
||||
"name": "Datasheet",
|
||||
"show": true
|
||||
},
|
||||
{
|
||||
"group_by": false,
|
||||
"label": "Footprint",
|
||||
"name": "Footprint",
|
||||
"show": true
|
||||
},
|
||||
{
|
||||
"group_by": false,
|
||||
"label": "Qty",
|
||||
"name": "${QUANTITY}",
|
||||
"show": true
|
||||
},
|
||||
{
|
||||
"group_by": true,
|
||||
"label": "DNP",
|
||||
"name": "${DNP}",
|
||||
"show": true
|
||||
}
|
||||
],
|
||||
"filter_string": "",
|
||||
"group_symbols": true,
|
||||
"name": "Grouped By Value",
|
||||
"sort_asc": true,
|
||||
"sort_field": "Reference"
|
||||
},
|
||||
"connection_grid_size": 50.0,
|
||||
"drawing": {
|
||||
"dashed_lines_dash_length_ratio": 12.0,
|
||||
"dashed_lines_gap_length_ratio": 3.0,
|
||||
"default_line_thickness": 6.0,
|
||||
"default_text_size": 50.0,
|
||||
"field_names": [],
|
||||
"intersheets_ref_own_page": false,
|
||||
"intersheets_ref_prefix": "",
|
||||
"intersheets_ref_short": false,
|
||||
"intersheets_ref_show": false,
|
||||
"intersheets_ref_suffix": "",
|
||||
"junction_size_choice": 3,
|
||||
"label_size_ratio": 0.25,
|
||||
"operating_point_overlay_i_precision": 3,
|
||||
"operating_point_overlay_i_range": "~A",
|
||||
"operating_point_overlay_v_precision": 3,
|
||||
"operating_point_overlay_v_range": "~V",
|
||||
"overbar_offset_ratio": 1.23,
|
||||
"pin_symbol_size": 0.0,
|
||||
"text_offset_ratio": 0.08
|
||||
},
|
||||
"legacy_lib_dir": "",
|
||||
"legacy_lib_list": [],
|
||||
"meta": {
|
||||
"version": 1
|
||||
},
|
||||
"net_format_name": "Spice",
|
||||
"ngspice": {
|
||||
"fix_include_paths": true,
|
||||
"fix_passive_vals": false,
|
||||
"meta": {
|
||||
"version": 0
|
||||
},
|
||||
"model_mode": 0,
|
||||
"workbook_filename": "power_supply.wbk"
|
||||
},
|
||||
"page_layout_descr_file": "",
|
||||
"plot_directory": "",
|
||||
"spice_adjust_passive_values": false,
|
||||
"spice_current_sheet_as_root": false,
|
||||
"spice_external_command": "C:\\Spice64\\bin\\ngspice \"%I\"",
|
||||
"spice_model_current_sheet_as_root": true,
|
||||
"spice_save_all_currents": false,
|
||||
"spice_save_all_dissipations": false,
|
||||
"spice_save_all_voltages": false,
|
||||
"subpart_first_id": 65,
|
||||
"subpart_id_separator": 0
|
||||
},
|
||||
"sheets": [
|
||||
[
|
||||
"32667662-ae86-4904-b198-3e95f11851bf",
|
||||
"Root"
|
||||
]
|
||||
],
|
||||
"text_variables": {}
|
||||
}
|
||||
LOADING design file
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue
Block a user