mirror of
https://gitlab.com/kicad/code/kicad.git
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Pcbnew: Enhanced algorithm to calculate board connections:
* A track is seen connected to a pad if the track end is inside the pad shape. * Pads inside pads are now seen connected, if the center of the pad is *inside* the other pad. * this is made to be sure a large copper area is shared by the 2 pads, and to keep algorithm fast.
This commit is contained in:
jean-pierre charras
parent
ccb910eb62
commit
d41b81fc3b
@ -4,6 +4,19 @@ KiCad ChangeLog 2011
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Please add newer entries at the top, list the date and your name with
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email address.
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2011-Dec-19, UPDATE Jean-Pierre Charras <jean-pierre.charras@gipsa-lab.inpg.fr>
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================================================================================
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Pcbnew:
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Enhanced algorithms to calculate board connections:
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- A track is seen connected to a pad if the track end is inside the pad shape.
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- Pads inside pads are now seen connected, if the center of the pad is
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*inside* the other pad.
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(this is made to be sure a large copper area is shared by the 2 pads,
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and to keep algorithm fast).
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Algorithm to calculate pads connections is still very fast.
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However some other functions (drag pads, track len calculation ...)
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still need the track end exactly on the pad position.
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2011-Dec-13 UPDATE Dick Hollenbeck <dick@softplc.com>
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================================================================================
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16
demos/test_pads_inside_pads/test_pads_inside_pads-cache.lib
Normal file
16
demos/test_pads_inside_pads/test_pads_inside_pads-cache.lib
Normal file
@ -0,0 +1,16 @@
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EESchema-LIBRARY Version 2.3 Date: 19/12/2011 12:55:30
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#encoding utf-8
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#
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# CONN_1
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#
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DEF ~CONN_1 P 0 30 N N 1 F N
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F0 "P" 80 0 40 H V L CNN
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F1 "CONN_1" 0 55 30 H I C CNN
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DRAW
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C 0 0 31 0 1 0 N
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P 2 0 1 0 -30 0 -50 0 N
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X 1 1 -150 0 100 R 60 60 1 1 P
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ENDDRAW
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ENDDEF
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#
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#End Library
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LOADING design file
31
demos/test_pads_inside_pads/test_pads_inside_pads.cmp
Normal file
31
demos/test_pads_inside_pads/test_pads_inside_pads.cmp
Normal file
@ -0,0 +1,31 @@
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Cmp-Mod V01 Created by CvPcb (2011-12-09 BZR 3290)-testing date = 11/12/2011 20:34:04
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BeginCmp
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TimeStamp = /4EDF7CC5;
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Reference = P1;
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ValeurCmp = CONN_1;
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IdModule = 1pin;
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EndCmp
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BeginCmp
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TimeStamp = /4EDF7CC0;
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Reference = P2;
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ValeurCmp = CONN_1;
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IdModule = 1pin;
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EndCmp
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BeginCmp
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TimeStamp = /4EE5056C;
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Reference = P3;
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ValeurCmp = CONN_1;
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IdModule = 1pin;
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EndCmp
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BeginCmp
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TimeStamp = /4EE5056D;
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Reference = P4;
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ValeurCmp = CONN_1;
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IdModule = 1pin;
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EndCmp
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EndListe
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25
demos/test_pads_inside_pads/test_pads_inside_pads.net
Normal file
25
demos/test_pads_inside_pads/test_pads_inside_pads.net
Normal file
@ -0,0 +1,25 @@
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# EESchema Netlist Version 1.1 created 19/12/2011 12:55:28
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(
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( /4EE5056D $noname P4 CONN_1 {Lib=CONN_1}
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( 1 /NET1 )
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)
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( /4EE5056C $noname P3 CONN_1 {Lib=CONN_1}
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( 1 /NET1 )
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)
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( /4EDF7CC5 $noname P1 CONN_1 {Lib=CONN_1}
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( 1 /NET2 )
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)
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( /4EDF7CC0 $noname P2 CONN_1 {Lib=CONN_1}
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( 1 /NET2 )
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)
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)
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*
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{ Pin List by Nets
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Net 1 "/NET1" "NET1"
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P4 1
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P3 1
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Net 2 "/NET2" "NET2"
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P1 1
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P2 1
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}
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#End
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108
demos/test_pads_inside_pads/test_pads_inside_pads.pro
Normal file
108
demos/test_pads_inside_pads/test_pads_inside_pads.pro
Normal file
@ -0,0 +1,108 @@
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update=13/12/2011 11:04:14
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version=1
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last_client=pcbnew
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[cvpcb]
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version=1
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NetITyp=0
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NetIExt=.net
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PkgIExt=.pkg
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NetDir=
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LibDir=
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NetType=0
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[cvpcb/libraries]
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EquName1=devcms
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[eeschema]
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version=1
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LibDir=
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NetFmt=1
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HPGLSpd=20
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HPGLDm=15
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HPGLNum=1
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offX_A4=0
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offY_A4=0
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offX_A3=0
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offY_A3=0
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offX_A2=0
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offY_A2=0
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offX_A1=0
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offY_A1=0
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offX_A0=0
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offY_A0=0
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offX_A=0
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offY_A=0
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offX_B=0
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offY_B=0
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offX_C=0
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offY_C=0
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offX_D=0
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offY_D=0
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offX_E=0
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offY_E=0
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RptD_X=0
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RptD_Y=100
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RptLab=1
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SimCmd=
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UseNetN=0
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LabSize=60
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[eeschema/libraries]
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LibName1=power
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LibName2=device
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LibName3=transistors
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LibName4=conn
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LibName5=linear
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LibName6=regul
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LibName7=74xx
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LibName8=cmos4000
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LibName9=adc-dac
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LibName10=memory
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LibName11=xilinx
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LibName12=special
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LibName13=microcontrollers
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LibName14=dsp
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LibName15=microchip
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LibName16=analog_switches
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LibName17=motorola
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LibName18=texas
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LibName19=intel
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LibName20=audio
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LibName21=interface
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LibName22=digital-audio
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LibName23=philips
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LibName24=display
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LibName25=cypress
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LibName26=siliconi
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LibName27=opto
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LibName28=atmel
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LibName29=contrib
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LibName30=valves
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[general]
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version=1
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[pcbnew]
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version=1
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PadDrlX=320
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PadDimH=600
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PadDimV=600
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BoardThickness=630
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TxtPcbV=800
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TxtPcbH=600
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TxtModV=600
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TxtModH=600
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TxtModW=120
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VEgarde=100
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DrawLar=150
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EdgeLar=150
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TxtLar=120
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MSegLar=150
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LastNetListRead=
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[pcbnew/libraries]
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LibDir=
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LibName1=sockets
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LibName2=connect
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LibName3=discret
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LibName4=pin_array
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LibName5=divers
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LibName6=libcms
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LibName7=display
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LibName8=valves
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LibName9=led
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LibName10=dip_sockets
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90
demos/test_pads_inside_pads/test_pads_inside_pads.sch
Normal file
90
demos/test_pads_inside_pads/test_pads_inside_pads.sch
Normal file
@ -0,0 +1,90 @@
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EESchema Schematic File Version 2 date 19/12/2011 12:55:30
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LIBS:power
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LIBS:device
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LIBS:transistors
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LIBS:conn
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LIBS:linear
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LIBS:regul
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||||
LIBS:74xx
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LIBS:cmos4000
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LIBS:adc-dac
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||||
LIBS:memory
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||||
LIBS:xilinx
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||||
LIBS:special
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||||
LIBS:microcontrollers
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LIBS:dsp
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||||
LIBS:microchip
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||||
LIBS:analog_switches
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LIBS:motorola
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LIBS:texas
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||||
LIBS:intel
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LIBS:audio
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||||
LIBS:interface
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||||
LIBS:digital-audio
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LIBS:philips
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||||
LIBS:display
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||||
LIBS:cypress
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LIBS:siliconi
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LIBS:opto
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LIBS:atmel
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LIBS:contrib
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LIBS:valves
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EELAYER 25 0
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EELAYER END
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$Descr A4 11700 8267
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encoding utf-8
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Sheet 1 1
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Title ""
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Date "19 dec 2011"
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Rev ""
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Comp ""
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Comment1 ""
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Comment2 ""
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Comment3 ""
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Comment4 ""
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$EndDescr
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Wire Wire Line
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4150 1750 3750 1750
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Wire Wire Line
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4150 1450 3750 1450
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Text Label 3850 1450 0 60 ~ 0
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NET1
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$Comp
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||||
L CONN_1 P4
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U 1 1 4EE5056D
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P 4300 1450
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F 0 "P4" H 4380 1450 40 0000 L CNN
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F 1 "CONN_1" H 4300 1505 30 0001 C CNN
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1 4300 1450
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||||
1 0 0 -1
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||||
$EndComp
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||||
$Comp
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||||
L CONN_1 P3
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||||
U 1 1 4EE5056C
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||||
P 3600 1450
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||||
F 0 "P3" H 3680 1450 40 0000 L CNN
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||||
F 1 "CONN_1" H 3600 1505 30 0001 C CNN
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||||
1 3600 1450
|
||||
-1 0 0 1
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||||
$EndComp
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||||
$Comp
|
||||
L CONN_1 P1
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||||
U 1 1 4EDF7CC5
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||||
P 3600 1750
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||||
F 0 "P1" H 3680 1750 40 0000 L CNN
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||||
F 1 "CONN_1" H 3600 1805 30 0001 C CNN
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||||
1 3600 1750
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||||
-1 0 0 1
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||||
$EndComp
|
||||
$Comp
|
||||
L CONN_1 P2
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||||
U 1 1 4EDF7CC0
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||||
P 4300 1750
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||||
F 0 "P2" H 4380 1750 40 0000 L CNN
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||||
F 1 "CONN_1" H 4300 1805 30 0001 C CNN
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||||
1 4300 1750
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||||
1 0 0 -1
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$EndComp
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||||
Text Label 3850 1750 0 60 ~ 0
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NET2
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$EndSCHEMATC
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@ -129,10 +129,9 @@ public:
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* Function BuildTracksCandidatesList
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* Fills m_Candidates with all connecting points (track ends or via location)
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* with tracks from aBegin to aEnd.
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* if aBegin == NULL, use first track in brd list
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* if aEnd == NULL, uses all tracks from aBegin in brd list
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* if aEnd == NULL, uses all tracks from aBegin
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*/
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void BuildTracksCandidatesList( TRACK * aBegin = NULL, TRACK * aEnd = NULL);
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void BuildTracksCandidatesList( TRACK * aBegin, TRACK * aEnd = NULL);
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/**
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* Function BuildPadsCandidatesList
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@ -209,15 +208,15 @@ public:
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private:
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/**
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* function searchEntryPoint
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* function searchEntryPointInCandidatesList
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* Search an item in m_Connected connected to aPoint
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* note m_Connected containts usually more than one candidate
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* and searchEntryPoint returns an index to one of these candidates
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* and searchEntryPointInCandidatesList returns an index to one of these candidates
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* Others are neightbor of the indexed item.
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* @param aPoint is the reference coordinates
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* @return the index of item found or -1 if no candidate
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*/
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int searchEntryPoint( const wxPoint & aPoint);
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int searchEntryPointInCandidatesList( const wxPoint & aPoint);
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/**
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* Function Merge_SubNets
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@ -438,10 +437,10 @@ void CONNECTIONS::BuildTracksCandidatesList( TRACK * aBegin, TRACK * aEnd)
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{
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m_candidates.clear();
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if( aBegin == NULL )
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aBegin = m_brd->m_Track;
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// if( aBegin == NULL )
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// aBegin = m_brd->m_Track;
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m_firstTrack = aBegin;
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m_firstTrack = m_lastTrack = aBegin;
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unsigned ii = 0;
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// Count candidates ( i.e. end points )
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@ -489,7 +488,7 @@ int CONNECTIONS::SearchConnectedTracks( const TRACK * aTrack )
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wxPoint position = aTrack->m_Start;
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for( int kk = 0; kk < 2; kk++ )
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{
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int idx = searchEntryPoint( position );
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int idx = searchEntryPointInCandidatesList( position );
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if ( idx >= 0 )
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{
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// search after:
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@ -524,7 +523,7 @@ int CONNECTIONS::SearchConnectedTracks( const TRACK * aTrack )
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return count;
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}
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int CONNECTIONS::searchEntryPoint( const wxPoint & aPoint)
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int CONNECTIONS::searchEntryPointInCandidatesList( const wxPoint & aPoint)
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{
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// Search the aPoint coordinates in m_Candidates
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// m_Candidates is sorted by X then Y values, and a fast binary search is used
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@ -582,6 +581,7 @@ int CONNECTIONS::searchEntryPoint( const wxPoint & aPoint)
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/* Used after a track change (delete a track ou add a track)
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* Connections to pads are recalculated
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* Note also aFirstTrack (and aLastTrack ) can be NULL
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*/
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void CONNECTIONS::Build_CurrNet_SubNets_Connections( TRACK* aFirstTrack, TRACK* aLastTrack, int aNetcode )
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{
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@ -611,6 +611,9 @@ void CONNECTIONS::Build_CurrNet_SubNets_Connections( TRACK* aFirstTrack, TRACK*
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BuildPadsList( aNetcode );
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SearchTracksConnectedToPads();
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// Update connections between intersecting pads (no tracks)
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SearchConnectionsPadsToIntersectingPads();
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// Creates sub nets (clusters) for the current net:
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Propagate_SubNets();
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}
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@ -705,13 +708,54 @@ int CONNECTIONS::Merge_SubNets( int aOldSubNet, int aNewSubNet )
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*/
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void CONNECTIONS::Propagate_SubNets()
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{
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TRACK* curr_track;
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int sub_netcode;
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int sub_netcode = 0;
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curr_track = (TRACK*)m_firstTrack;
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sub_netcode = 1;
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curr_track->SetSubNet( sub_netcode );
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// Examine connections between intersecting pads
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for( unsigned ii = 0; ii < m_sortedPads.size(); ii++ )
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{
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D_PAD * curr_pad = m_sortedPads[ii];
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for( unsigned jj = 0; jj < curr_pad->m_PadsConnected.size(); jj++ )
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{
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D_PAD * pad = curr_pad->m_PadsConnected[jj];
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if( curr_pad->GetSubNet() )
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{
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if( pad->GetSubNet() > 0 )
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{
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// The pad is already a cluster member, so we can merge the 2 clusters
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Merge_PadsSubNets( pad->GetSubNet(), curr_pad->GetSubNet() );
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}
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else
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{
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// The pad is not yet attached to a cluster,
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// so we can add this pad to the cluster
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pad->SetSubNet( curr_pad->GetSubNet() );
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}
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}
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else /* the track segment is not attached to a cluster */
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||||
{
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||||
if( pad->GetSubNet() > 0 )
|
||||
{
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||||
// it is connected to a pad in a cluster, merge this pad
|
||||
curr_pad->SetSubNet( pad->GetSubNet() );
|
||||
}
|
||||
else
|
||||
{
|
||||
// it is connected to a pad not in a cluster,
|
||||
// so we must create a new cluster (only with the 2 pads.
|
||||
sub_netcode++;
|
||||
curr_pad->SetSubNet( sub_netcode );
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||||
pad->SetSubNet( curr_pad->GetSubNet() );
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||||
}
|
||||
}
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||||
}
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||||
}
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||||
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||||
sub_netcode++;
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TRACK* curr_track = (TRACK*)m_firstTrack;
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if( curr_track )
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curr_track->SetSubNet( sub_netcode );
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||||
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||||
// Examine connections between trcaks and pads
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for( ; curr_track != NULL; curr_track = curr_track->Next() )
|
||||
{
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||||
/* First: handling connections to pads */
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||||
@ -793,6 +837,12 @@ void CONNECTIONS::Propagate_SubNets()
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||||
}
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||||
}
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||||
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/*
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* Test all connections of the board,
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* and update subnet variable of pads and tracks
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||||
* TestForActiveLinksInRatsnest must be called after this function
|
||||
* to update active/inactive ratsnest items status
|
||||
*/
|
||||
void PCB_BASE_FRAME::TestConnections()
|
||||
{
|
||||
// Clear the cluster identifier for all pads
|
||||
@ -806,21 +856,41 @@ void PCB_BASE_FRAME::TestConnections()
|
||||
|
||||
m_Pcb->Test_Connections_To_Copper_Areas();
|
||||
|
||||
// int st = clock(); // For test only, will be removed
|
||||
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||||
// Test existing connections net by net
|
||||
// note some nets can have no tracks, and pads intersecting
|
||||
// so Build_CurrNet_SubNets_Connections must be called for each net
|
||||
CONNECTIONS connections( m_Pcb );
|
||||
int last_net_tested = 0;
|
||||
int current_net_code = 0;
|
||||
for( TRACK* track = m_Pcb->m_Track; track; )
|
||||
{
|
||||
// At this point, track is the first track of a given net
|
||||
int current_net_code = track->GetNet();
|
||||
current_net_code = track->GetNet();
|
||||
// Get last track of the current net
|
||||
TRACK* lastTrack = track->GetEndNetCode( current_net_code );
|
||||
|
||||
if( current_net_code > 0 ) // do not spend time if net code = 0 ( dummy net )
|
||||
{
|
||||
// Test all previous nets having no tracks
|
||||
for( int net = last_net_tested+1; net < current_net_code; net++ )
|
||||
connections.Build_CurrNet_SubNets_Connections( NULL, NULL, net );
|
||||
|
||||
connections.Build_CurrNet_SubNets_Connections( track, lastTrack, current_net_code );
|
||||
last_net_tested = current_net_code;
|
||||
}
|
||||
|
||||
track = lastTrack->Next(); // this is now the first track of the next net
|
||||
}
|
||||
|
||||
// Test last nets without tracks, if any
|
||||
int netsCount = m_Pcb->GetNetCount();
|
||||
for( int net = last_net_tested+1; net < netsCount; net++ )
|
||||
connections.Build_CurrNet_SubNets_Connections( NULL, NULL, net );
|
||||
|
||||
// wxLogMessage("time %g ms", (double)(clock() - st)*1000.0/CLOCKS_PER_SEC);
|
||||
|
||||
Merge_SubNets_Connected_By_CopperAreas( m_Pcb );
|
||||
|
||||
return;
|
||||
@ -925,7 +995,7 @@ void PCB_BASE_FRAME::RecalculateAllTracksNetcode()
|
||||
|
||||
CONNECTIONS connections( m_Pcb );
|
||||
connections.BuildPadsList();
|
||||
connections.BuildTracksCandidatesList();
|
||||
connections.BuildTracksCandidatesList(m_Pcb->m_Track);
|
||||
|
||||
// First pass: build connections between track segments and pads.
|
||||
connections.SearchTracksConnectedToPads();
|
||||
|
||||
Loading…
Reference in New Issue
Block a user