From e0453d9bccb06e4d5c6ca24bca198b8121d8eb11 Mon Sep 17 00:00:00 2001
From: Seth Hillbrand <seth@kipro-pcb.com>
Date: Mon, 8 Jul 2024 22:00:53 -0700
Subject: [PATCH] Further cleanup of LSET
Remove duplicative functions. Standardize on C++ stdlib formatting
---
common/lset.cpp | 125 +++---------------
gerbview/gerbview_frame.h | 2 +-
gerbview/gerbview_printout.h | 2 +-
include/lset.h | 35 +----
include/pcb_base_frame.h | 2 +-
kicad/cli/command_pcb_export_base.cpp | 20 +--
pcbnew/autorouter/ar_matrix.h | 2 +-
.../board_stackup_manager/board_stackup.cpp | 2 +-
pcbnew/board_stackup_manager/board_stackup.h | 2 +-
pcbnew/dialogs/dialog_plot.cpp | 2 +-
pcbnew/dialogs/dialog_print_pcbnew.cpp | 2 +-
pcbnew/drc/drc_engine.cpp | 6 +-
.../drc/drc_test_provider_edge_clearance.cpp | 2 +-
.../drc_test_provider_physical_clearance.cpp | 2 +-
.../drc/drc_test_provider_silk_clearance.cpp | 8 +-
pcbnew/drc/drc_test_provider_solder_mask.cpp | 8 +-
pcbnew/pad.cpp | 10 +-
pcbnew/pcb_edit_frame.cpp | 2 +-
pcbnew/pcb_io/altium/altium_pcb.cpp | 2 +-
.../cadstar/cadstar_pcb_archive_loader.cpp | 24 ++--
pcbnew/pcb_io/eagle/pcb_io_eagle.cpp | 6 +-
.../pcb_io/easyeda/pcb_io_easyeda_parser.cpp | 2 +-
pcbnew/pcb_io/geda/pcb_io_geda.cpp | 6 +-
pcbnew/pcb_io/ipc2581/pcb_io_ipc2581.cpp | 4 +-
.../pcb_io/kicad_sexpr/pcb_io_kicad_sexpr.cpp | 14 +-
.../pcb_io/kicad_sexpr/pcb_io_kicad_sexpr.h | 2 +-
.../kicad_sexpr/pcb_io_kicad_sexpr_parser.cpp | 14 +-
pcbnew/pcb_io/pcad/pcad_pad.cpp | 8 +-
pcbnew/pcb_plot_params.cpp | 6 +-
pcbnew/plot_board_layers.cpp | 4 +-
pcbnew/plotcontroller.h | 2 +-
pcbnew/tools/pcb_grid_helper.h | 2 +-
pcbnew/tools/pcb_selection_tool.cpp | 4 +-
qa/tests/pcbnew/test_lset.cpp | 4 +-
34 files changed, 109 insertions(+), 229 deletions(-)
diff --git a/common/lset.cpp b/common/lset.cpp
index 7a60bf2087..70762c7962 100644
--- a/common/lset.cpp
+++ b/common/lset.cpp
@@ -39,41 +39,11 @@
#include <lset.h>
-LSET::LSET( const PCB_LAYER_ID* aArray, unsigned aCount ) :
+LSET::LSET( std::initializer_list<PCB_LAYER_ID> aList ) :
BASE_SET()
{
- for( unsigned i=0; i<aCount; ++i )
- set( aArray[i] );
-}
-
-
-LSET::LSET( unsigned aIdCount, int aFirst, ... ) :
- BASE_SET()
-{
- // The constructor, without the mandatory aFirst argument, could have been confused
- // by the compiler with the LSET( PCB_LAYER_ID ). With aFirst, that ambiguity is not
- // present. Therefore aIdCount must always be >=1.
- wxASSERT_MSG( aIdCount > 0, wxT( "aIdCount must be >= 1" ) );
-
- set( aFirst );
-
- if( --aIdCount )
- {
- va_list ap;
-
- va_start( ap, aFirst );
-
- for( unsigned i=0; i<aIdCount; ++i )
- {
- PCB_LAYER_ID id = (PCB_LAYER_ID) va_arg( ap, int );
-
- assert( unsigned( id ) < PCB_LAYER_ID_COUNT );
-
- set( id );
- }
-
- va_end( ap );
- }
+ for( PCB_LAYER_ID layer : aList )
+ set( layer );
}
@@ -741,68 +711,25 @@ PCB_LAYER_ID LSET::ExtractLayer() const
LSET LSET::FrontAssembly()
{
- static const PCB_LAYER_ID front_assembly[] = {
- F_SilkS,
- F_Mask,
- F_Fab,
- F_CrtYd
- };
-
- static const LSET saved( front_assembly, arrayDim( front_assembly ) );
+ static const LSET saved( { F_SilkS, F_Mask, F_Fab, F_CrtYd } );
return saved;
}
LSET LSET::BackAssembly()
{
- static const PCB_LAYER_ID back_assembly[] = {
- B_SilkS,
- B_Mask,
- B_Fab,
- B_CrtYd
- };
-
- static const LSET saved( back_assembly, arrayDim( back_assembly ) );
+ static const LSET saved( { B_SilkS, B_Mask, B_Fab, B_CrtYd } );
return saved;
}
LSET LSET::InternalCuMask()
{
- static const PCB_LAYER_ID cu_internals[] = {
- In1_Cu,
- In2_Cu,
- In3_Cu,
- In4_Cu,
- In5_Cu,
- In6_Cu,
- In7_Cu,
- In8_Cu,
- In9_Cu,
- In10_Cu,
- In11_Cu,
- In12_Cu,
- In13_Cu,
- In14_Cu,
- In15_Cu,
- In16_Cu,
- In17_Cu,
- In18_Cu,
- In19_Cu,
- In20_Cu,
- In21_Cu,
- In22_Cu,
- In23_Cu,
- In24_Cu,
- In25_Cu,
- In26_Cu,
- In27_Cu,
- In28_Cu,
- In29_Cu,
- In30_Cu,
- };
-
- static const LSET saved( cu_internals, arrayDim( cu_internals ) );
+ static const LSET saved( { In1_Cu, In2_Cu, In3_Cu, In4_Cu, In5_Cu, In6_Cu,
+ In7_Cu, In8_Cu, In9_Cu, In10_Cu, In11_Cu, In12_Cu,
+ In13_Cu, In14_Cu, In15_Cu, In16_Cu, In17_Cu, In18_Cu,
+ In19_Cu, In20_Cu, In21_Cu, In22_Cu, In23_Cu, In24_Cu,
+ In25_Cu, In26_Cu, In27_Cu, In28_Cu, In29_Cu, In30_Cu } );
return saved;
}
@@ -837,7 +764,7 @@ LSET LSET::AllNonCuMask()
LSET LSET::ExternalCuMask()
{
- static const LSET saved( 2, F_Cu, B_Cu );
+ static const LSET saved( { F_Cu, B_Cu } );
return saved;
}
@@ -851,26 +778,26 @@ LSET LSET::AllLayersMask()
LSET LSET::BackTechMask()
{
- static const LSET saved( 6, B_SilkS, B_Mask, B_Adhes, B_Paste, B_CrtYd, B_Fab );
+ static const LSET saved( { B_SilkS, B_Mask, B_Adhes, B_Paste, B_CrtYd, B_Fab } );
return saved;
}
LSET LSET::BackBoardTechMask()
{
- static const LSET saved( 4, B_SilkS, B_Mask, B_Adhes, B_Paste );
+ static const LSET saved( { B_SilkS, B_Mask, B_Adhes, B_Paste } );
return saved;
}
LSET LSET::FrontTechMask()
{
- static const LSET saved( 6, F_SilkS, F_Mask, F_Adhes, F_Paste, F_CrtYd, F_Fab );
+ static const LSET saved( { F_SilkS, F_Mask, F_Adhes, F_Paste, F_CrtYd, F_Fab } );
return saved;
}
LSET LSET::FrontBoardTechMask()
{
- static const LSET saved( 4, F_SilkS, F_Mask, F_Adhes, F_Paste );
+ static const LSET saved( { F_SilkS, F_Mask, F_Adhes, F_Paste } );
return saved;
}
@@ -891,14 +818,7 @@ LSET LSET::AllBoardTechMask()
LSET LSET::UserMask()
{
- static const LSET saved( 6,
- Dwgs_User,
- Cmts_User,
- Eco1_User,
- Eco2_User,
- Edge_Cuts,
- Margin
- );
+ static const LSET saved( { Dwgs_User, Cmts_User, Eco1_User, Eco2_User, Edge_Cuts, Margin } );
return saved;
}
@@ -913,17 +833,8 @@ LSET LSET::PhysicalLayersMask()
LSET LSET::UserDefinedLayers()
{
- static const LSET saved( 9,
- User_1,
- User_2,
- User_3,
- User_4,
- User_5,
- User_6,
- User_7,
- User_8,
- User_9
- );
+ static const LSET saved(
+ { User_1, User_2, User_3, User_4, User_5, User_6, User_7, User_8, User_9 } );
return saved;
}
diff --git a/gerbview/gerbview_frame.h b/gerbview/gerbview_frame.h
index 57eee5f549..4df6b76252 100644
--- a/gerbview/gerbview_frame.h
+++ b/gerbview/gerbview_frame.h
@@ -24,7 +24,6 @@
#include <file_history.h>
#include <eda_draw_frame.h>
-#include <lset.h>
#include <layer_ids.h>
#include <gerbview.h>
#include <gbr_layout.h>
@@ -40,6 +39,7 @@ class GERBER_DRAW_ITEM;
class GERBER_FILE_IMAGE;
class GERBER_FILE_IMAGE_LIST;
class GERBVIEW_SETTINGS;
+class LSET;
class REPORTER;
class SELECTION;
class wxStaticText;
diff --git a/gerbview/gerbview_printout.h b/gerbview/gerbview_printout.h
index 3d5f3edbb7..44e2003dbe 100644
--- a/gerbview/gerbview_printout.h
+++ b/gerbview/gerbview_printout.h
@@ -20,10 +20,10 @@
#ifndef GERBVIEW_PRINTOUT_H
#define GERBVIEW_PRINTOUT_H
-#include <lset.h>
#include <board_printout.h>
class GBR_LAYOUT;
+class LSET;
class GERBVIEW_PRINTOUT : public BOARD_PRINTOUT
{
diff --git a/include/lset.h b/include/lset.h
index dadb2b1b91..0f7a359fd8 100644
--- a/include/lset.h
+++ b/include/lset.h
@@ -27,7 +27,6 @@
class LSEQ;
typedef std::bitset<PCB_LAYER_ID_COUNT> BASE_SET;
-
/**
* LSET is a set of PCB_LAYER_IDs. It can be converted to numerous purpose LSEQs using
* the various member functions, most of which are based on Seq(). The advantage
@@ -61,43 +60,13 @@ public:
{
}
- /**
- * Take a PCB_LAYER_ID and sets that bit. This makes the following code into
- * a bug:
- *
- * <code> LSET s = 0; </code>
- *
- * Instead use:
- *
- * <code>
- * LSET s;
- * </code>
- *
- * for an empty set.
- */
- LSET( PCB_LAYER_ID aLayer ) : // PCB_LAYER_ID deliberately excludes int and relatives
+ LSET( PCB_LAYER_ID aLayer ) :
BASE_SET()
{
set( aLayer );
}
- /**
- * Create an array or LSEQ.
- */
- LSET( const PCB_LAYER_ID* aArray, unsigned aCount );
-
- /**
- * Take one or more PCB_LAYER_IDs in the argument list to construct the set. Typically
- * only used in static construction.
- *
- * @param aIdCount is the number of PCB_LAYER_IDs which follow.
- * @param aFirst is the first included in @a aIdCount and must always be present, and can
- * be followed by any number of additional PCB_LAYER_IDs so long as @a aIdCount accurately
- * reflects the count.
- *
- * Parameter is 'int' to avoid va_start undefined behavior.
- */
- LSET( unsigned aIdCount, int aFirst, ... ); // args chosen to prevent LSET( int ) from compiling
+ LSET( std::initializer_list<PCB_LAYER_ID> aList );
LSET( const LSEQ& aSeq );
diff --git a/include/pcb_base_frame.h b/include/pcb_base_frame.h
index 85dc5b2f18..bb3a759c92 100644
--- a/include/pcb_base_frame.h
+++ b/include/pcb_base_frame.h
@@ -31,7 +31,6 @@
#include <eda_draw_frame.h>
#include <outline_mode.h>
#include <lib_id.h>
-#include <lset.h>
#include <pcb_display_options.h>
#include <pcb_draw_panel_gal.h>
#include <pcb_origin_transforms.h>
@@ -53,6 +52,7 @@ class EDA_3D_VIEWER_FRAME;
class GENERAL_COLLECTOR;
class GENERAL_COLLECTORS_GUIDE;
class BOARD_DESIGN_SETTINGS;
+class LSET;
class ZONE_SETTINGS;
class PCB_PLOT_PARAMS;
class FP_LIB_TABLE;
diff --git a/kicad/cli/command_pcb_export_base.cpp b/kicad/cli/command_pcb_export_base.cpp
index 54d0e58d87..57a19c249a 100644
--- a/kicad/cli/command_pcb_export_base.cpp
+++ b/kicad/cli/command_pcb_export_base.cpp
@@ -59,18 +59,18 @@ CLI::PCB_EXPORT_BASE_COMMAND::PCB_EXPORT_BASE_COMMAND( const std::string& aName,
m_layerMasks["*"] = LSET::AllLayersMask();
m_layerMasks["*.Cu"] = LSET::AllCuMask();
m_layerMasks["*In.Cu"] = LSET::InternalCuMask();
- m_layerMasks["F&B.Cu"] = LSET( 2, F_Cu, B_Cu );
- m_layerMasks["*.Adhes"] = LSET( 2, B_Adhes, F_Adhes );
- m_layerMasks["*.Paste"] = LSET( 2, B_Paste, F_Paste );
- m_layerMasks["*.Mask"] = LSET( 2, B_Mask, F_Mask );
- m_layerMasks["*.SilkS"] = LSET( 2, B_SilkS, F_SilkS );
- m_layerMasks["*.Fab"] = LSET( 2, B_Fab, F_Fab );
- m_layerMasks["*.CrtYd"] = LSET( 2, B_CrtYd, F_CrtYd );
+ m_layerMasks["F&B.Cu"] = LSET( { F_Cu, B_Cu } );
+ m_layerMasks["*.Adhes"] = LSET( { B_Adhes, F_Adhes } );
+ m_layerMasks["*.Paste"] = LSET( { B_Paste, F_Paste } );
+ m_layerMasks["*.Mask"] = LSET( { B_Mask, F_Mask } );
+ m_layerMasks["*.SilkS"] = LSET( { B_SilkS, F_SilkS } );
+ m_layerMasks["*.Fab"] = LSET( { B_Fab, F_Fab } );
+ m_layerMasks["*.CrtYd"] = LSET( { B_CrtYd, F_CrtYd } );
// Add list of grouped layer names using GUI canonical layer names
- m_layerGuiMasks["*.Adhesive"] = LSET( 2, B_Adhes, F_Adhes );
- m_layerGuiMasks["*.Silkscreen"] = LSET( 2, B_SilkS, F_SilkS );
- m_layerGuiMasks["*.Courtyard"] = LSET( 2, B_CrtYd, F_CrtYd );
+ m_layerGuiMasks["*.Adhesive"] = LSET( { B_Adhes, F_Adhes } );
+ m_layerGuiMasks["*.Silkscreen"] = LSET( { B_SilkS, F_SilkS } );
+ m_layerGuiMasks["*.Courtyard"] = LSET( { B_CrtYd, F_CrtYd } );
}
diff --git a/pcbnew/autorouter/ar_matrix.h b/pcbnew/autorouter/ar_matrix.h
index dc0a0dde66..4e15b56715 100644
--- a/pcbnew/autorouter/ar_matrix.h
+++ b/pcbnew/autorouter/ar_matrix.h
@@ -30,12 +30,12 @@
#define __AR_MATRIX_H
#include <layer_ids.h>
-#include <lset.h>
#include <math/box2.h>
class PCB_SHAPE;
class PAD;
class FOOTPRINT;
+class LSET;
#define AR_MAX_ROUTING_LAYERS_COUNT 2
diff --git a/pcbnew/board_stackup_manager/board_stackup.cpp b/pcbnew/board_stackup_manager/board_stackup.cpp
index e27f920678..5ff37a9556 100644
--- a/pcbnew/board_stackup_manager/board_stackup.cpp
+++ b/pcbnew/board_stackup_manager/board_stackup.cpp
@@ -619,7 +619,7 @@ void BOARD_STACKUP::BuildDefaultStackupList( const BOARD_DESIGN_SETTINGS* aSetti
( BOARD_STACKUP_ITEM::GetCopperDefaultThickness() * activeCuLayerCount );
// Take in account the solder mask thickness:
- int sm_count = ( enabledLayer & LSET( 2, F_Mask, B_Mask) ).count();
+ int sm_count = ( enabledLayer & LSET( { F_Mask, B_Mask } ) ).count();
diel_thickness -= BOARD_STACKUP_ITEM::GetMaskDefaultThickness() * sm_count;
diel_thickness /= std::max( 1, activeCuLayerCount - 1 );
diff --git a/pcbnew/board_stackup_manager/board_stackup.h b/pcbnew/board_stackup_manager/board_stackup.h
index dcfca399c3..dbaef41e8b 100644
--- a/pcbnew/board_stackup_manager/board_stackup.h
+++ b/pcbnew/board_stackup_manager/board_stackup.h
@@ -242,7 +242,7 @@ public:
*/
static LSET StackupAllowedBrdLayers()
{
- return LSET( 6, F_SilkS, F_Mask, F_Paste, B_SilkS, B_Mask, B_Paste )
+ return LSET( { F_SilkS, F_Mask, F_Paste, B_SilkS, B_Mask, B_Paste } )
| LSET::ExternalCuMask() | LSET::InternalCuMask();
}
diff --git a/pcbnew/dialogs/dialog_plot.cpp b/pcbnew/dialogs/dialog_plot.cpp
index d0e1e4e1ae..a3a0c6a99b 100644
--- a/pcbnew/dialogs/dialog_plot.cpp
+++ b/pcbnew/dialogs/dialog_plot.cpp
@@ -466,7 +466,7 @@ void DIALOG_PLOT::arrangeAllLayersList( const LSEQ& aSeq )
void DIALOG_PLOT::OnRightClickLayers( wxMouseEvent& event )
{
// Build a list of layers for usual fabrication: copper layers + tech layers without courtyard
- LSET fab_layer_set = ( LSET::AllCuMask() | LSET::AllTechMask() ) & ~LSET( 2, B_CrtYd, F_CrtYd );
+ LSET fab_layer_set = ( LSET::AllCuMask() | LSET::AllTechMask() ) & ~LSET( { B_CrtYd, F_CrtYd } );
wxMenu menu;
menu.Append( new wxMenuItem( &menu, ID_LAYER_FAB, _( "Select Fab Layers" ) ) );
diff --git a/pcbnew/dialogs/dialog_print_pcbnew.cpp b/pcbnew/dialogs/dialog_print_pcbnew.cpp
index 1dd4814593..c968be4550 100644
--- a/pcbnew/dialogs/dialog_print_pcbnew.cpp
+++ b/pcbnew/dialogs/dialog_print_pcbnew.cpp
@@ -351,7 +351,7 @@ void DIALOG_PRINT_PCBNEW::onColorModeClicked( wxCommandEvent& event )
void DIALOG_PRINT_PCBNEW::onPopUpLayers( wxCommandEvent& event )
{
// Build a list of layers for usual fabrication: copper layers + tech layers without courtyard
- LSET fab_layer_set = ( LSET::AllCuMask() | LSET::AllTechMask() ) & ~LSET( 2, B_CrtYd, F_CrtYd );
+ LSET fab_layer_set = ( LSET::AllCuMask() | LSET::AllTechMask() ) & ~LSET( { B_CrtYd, F_CrtYd } );
switch( event.GetId() )
{
diff --git a/pcbnew/drc/drc_engine.cpp b/pcbnew/drc/drc_engine.cpp
index 3a40330379..9c7c85eb80 100644
--- a/pcbnew/drc/drc_engine.cpp
+++ b/pcbnew/drc/drc_engine.cpp
@@ -175,19 +175,19 @@ void DRC_ENGINE::loadImplicitRules()
rule->AddConstraint( thermalSpokeCountConstraint );
rule = createImplicitRule( _( "board setup constraints silk" ) );
- rule->m_LayerCondition = LSET( 2, F_SilkS, B_SilkS );
+ rule->m_LayerCondition = LSET( { F_SilkS, B_SilkS } );
DRC_CONSTRAINT silkClearanceConstraint( SILK_CLEARANCE_CONSTRAINT );
silkClearanceConstraint.Value().SetMin( bds.m_SilkClearance );
rule->AddConstraint( silkClearanceConstraint );
rule = createImplicitRule( _( "board setup constraints silk text height" ) );
- rule->m_LayerCondition = LSET( 2, F_SilkS, B_SilkS );
+ rule->m_LayerCondition = LSET( { F_SilkS, B_SilkS } );
DRC_CONSTRAINT silkTextHeightConstraint( TEXT_HEIGHT_CONSTRAINT );
silkTextHeightConstraint.Value().SetMin( bds.m_MinSilkTextHeight );
rule->AddConstraint( silkTextHeightConstraint );
rule = createImplicitRule( _( "board setup constraints silk text thickness" ) );
- rule->m_LayerCondition = LSET( 2, F_SilkS, B_SilkS );
+ rule->m_LayerCondition = LSET( { F_SilkS, B_SilkS } );
DRC_CONSTRAINT silkTextThicknessConstraint( TEXT_THICKNESS_CONSTRAINT );
silkTextThicknessConstraint.Value().SetMin( bds.m_MinSilkTextThickness );
rule->AddConstraint( silkTextThicknessConstraint );
diff --git a/pcbnew/drc/drc_test_provider_edge_clearance.cpp b/pcbnew/drc/drc_test_provider_edge_clearance.cpp
index 541403fd7a..9e4dec8497 100644
--- a/pcbnew/drc/drc_test_provider_edge_clearance.cpp
+++ b/pcbnew/drc/drc_test_provider_edge_clearance.cpp
@@ -177,7 +177,7 @@ bool DRC_TEST_PROVIDER_EDGE_CLEARANCE::Run()
std::vector<std::unique_ptr<PCB_SHAPE>> edges;
DRC_RTREE edgesTree;
- forEachGeometryItem( { PCB_SHAPE_T }, LSET( 2, Edge_Cuts, Margin ),
+ forEachGeometryItem( { PCB_SHAPE_T }, LSET( { Edge_Cuts, Margin } ),
[&]( BOARD_ITEM *item ) -> bool
{
PCB_SHAPE* shape = static_cast<PCB_SHAPE*>( item );
diff --git a/pcbnew/drc/drc_test_provider_physical_clearance.cpp b/pcbnew/drc/drc_test_provider_physical_clearance.cpp
index 22997d9904..05a05babca 100644
--- a/pcbnew/drc/drc_test_provider_physical_clearance.cpp
+++ b/pcbnew/drc/drc_test_provider_physical_clearance.cpp
@@ -117,7 +117,7 @@ bool DRC_TEST_PROVIDER_PHYSICAL_CLEARANCE::Run()
PCB_DIMENSION_T
};
- static const LSET courtyards( 2, F_CrtYd, B_CrtYd );
+ static const LSET courtyards( { F_CrtYd, B_CrtYd } );
//
// Generate a count for use in progress reporting.
diff --git a/pcbnew/drc/drc_test_provider_silk_clearance.cpp b/pcbnew/drc/drc_test_provider_silk_clearance.cpp
index 1411a0909c..20a917f8e5 100644
--- a/pcbnew/drc/drc_test_provider_silk_clearance.cpp
+++ b/pcbnew/drc/drc_test_provider_silk_clearance.cpp
@@ -135,16 +135,16 @@ bool DRC_TEST_PROVIDER_SILK_CLEARANCE::Run()
return true;
};
- forEachGeometryItem( s_allBasicItems, LSET( 2, F_SilkS, B_SilkS ), countItems );
+ forEachGeometryItem( s_allBasicItems, LSET( { F_SilkS, B_SilkS } ), countItems );
forEachGeometryItem( s_allBasicItems,
- LSET::FrontMask() | LSET::BackMask() | LSET( 2, Edge_Cuts, Margin ),
+ LSET::FrontMask() | LSET::BackMask() | LSET( { Edge_Cuts, Margin } ),
countItems );
- forEachGeometryItem( s_allBasicItems, LSET( 2, F_SilkS, B_SilkS ), addToSilkTree );
+ forEachGeometryItem( s_allBasicItems, LSET( { F_SilkS, B_SilkS } ), addToSilkTree );
forEachGeometryItem( s_allBasicItems,
- LSET::FrontMask() | LSET::BackMask() | LSET( 2, Edge_Cuts, Margin ),
+ LSET::FrontMask() | LSET::BackMask() | LSET( { Edge_Cuts, Margin } ),
addToTargetTree );
reportAux( wxT( "Testing %d silkscreen features against %d board items." ),
diff --git a/pcbnew/drc/drc_test_provider_solder_mask.cpp b/pcbnew/drc/drc_test_provider_solder_mask.cpp
index adc6501df1..19f72fbe5f 100644
--- a/pcbnew/drc/drc_test_provider_solder_mask.cpp
+++ b/pcbnew/drc/drc_test_provider_solder_mask.cpp
@@ -193,7 +193,7 @@ void DRC_TEST_PROVIDER_SOLDER_MASK::addItemToRTrees( BOARD_ITEM* aItem )
void DRC_TEST_PROVIDER_SOLDER_MASK::buildRTrees()
{
ZONE* solderMask = m_board->m_SolderMaskBridges;
- LSET layers = { 4, F_Mask, B_Mask, F_Cu, B_Cu };
+ LSET layers( { F_Mask, B_Mask, F_Cu, B_Cu } );
const size_t progressDelta = 500;
int count = 0;
@@ -245,7 +245,7 @@ void DRC_TEST_PROVIDER_SOLDER_MASK::buildRTrees()
void DRC_TEST_PROVIDER_SOLDER_MASK::testSilkToMaskClearance()
{
- LSET silkLayers = { 2, F_SilkS, B_SilkS };
+ LSET silkLayers( { F_SilkS, B_SilkS } );
const size_t progressDelta = 250;
int count = 0;
@@ -345,7 +345,7 @@ bool isMaskAperture( BOARD_ITEM* aItem )
if( aItem->Type() == PCB_PAD_T && static_cast<PAD*>( aItem )->IsFreePad() )
return true;
- static const LSET saved( 2, F_Mask, B_Mask );
+ static const LSET saved( { F_Mask, B_Mask } );
LSET maskLayers = aItem->GetLayerSet() & saved;
LSET copperLayers = ( aItem->GetLayerSet() & ~saved ) & LSET::AllCuMask();
@@ -703,7 +703,7 @@ void DRC_TEST_PROVIDER_SOLDER_MASK::testMaskItemAgainstZones( BOARD_ITEM* aItem,
void DRC_TEST_PROVIDER_SOLDER_MASK::testMaskBridges()
{
- LSET copperAndMaskLayers = { 4, F_Mask, B_Mask, F_Cu, B_Cu };
+ LSET copperAndMaskLayers( { F_Mask, B_Mask, F_Cu, B_Cu } );
const size_t progressDelta = 250;
int count = 0;
diff --git a/pcbnew/pad.cpp b/pcbnew/pad.cpp
index 2c3256d453..7b55ae5500 100644
--- a/pcbnew/pad.cpp
+++ b/pcbnew/pad.cpp
@@ -285,35 +285,35 @@ bool PAD::IsFreePad() const
LSET PAD::PTHMask()
{
- static LSET saved = LSET::AllCuMask() | LSET( 2, F_Mask, B_Mask );
+ static LSET saved = LSET::AllCuMask() | LSET( { F_Mask, B_Mask } );
return saved;
}
LSET PAD::SMDMask()
{
- static LSET saved( 3, F_Cu, F_Paste, F_Mask );
+ static LSET saved( { F_Cu, F_Paste, F_Mask } );
return saved;
}
LSET PAD::ConnSMDMask()
{
- static LSET saved( 2, F_Cu, F_Mask );
+ static LSET saved( { F_Cu, F_Mask } );
return saved;
}
LSET PAD::UnplatedHoleMask()
{
- static LSET saved = LSET( 4, F_Cu, B_Cu, F_Mask, B_Mask );
+ static LSET saved = LSET( { F_Cu, B_Cu, F_Mask, B_Mask } );
return saved;
}
LSET PAD::ApertureMask()
{
- static LSET saved( 1, F_Paste );
+ static LSET saved( F_Paste );
return saved;
}
diff --git a/pcbnew/pcb_edit_frame.cpp b/pcbnew/pcb_edit_frame.cpp
index f071df267e..4ac4a1e04b 100644
--- a/pcbnew/pcb_edit_frame.cpp
+++ b/pcbnew/pcb_edit_frame.cpp
@@ -1271,7 +1271,7 @@ void PCB_EDIT_FRAME::ShowBoardSetupDialog( const wxString& aInitialPage )
Prj().IncrementNetclassesTicker();
PCBNEW_SETTINGS* settings = GetPcbNewSettings();
- static LSET maskAndPasteLayers = LSET( 4, F_Mask, F_Paste, B_Mask, B_Paste );
+ static LSET maskAndPasteLayers = LSET( { F_Mask, F_Paste, B_Mask, B_Paste } );
GetCanvas()->GetView()->UpdateAllItemsConditionally(
[&]( KIGFX::VIEW_ITEM* aItem ) -> int
diff --git a/pcbnew/pcb_io/altium/altium_pcb.cpp b/pcbnew/pcb_io/altium/altium_pcb.cpp
index dfdaa5dfba..8c82926774 100644
--- a/pcbnew/pcb_io/altium/altium_pcb.cpp
+++ b/pcbnew/pcb_io/altium/altium_pcb.cpp
@@ -3433,7 +3433,7 @@ void ALTIUM_PCB::ConvertPads6ToFootprintItemOnCopper( FOOTPRINT* aFootprint, con
default:
PCB_LAYER_ID klayer = GetKicadLayer( aElem.layer );
pad->SetLayer( klayer );
- pad->SetLayerSet( LSET( 1, klayer ) );
+ pad->SetLayerSet( LSET( klayer ) );
break;
}
diff --git a/pcbnew/pcb_io/cadstar/cadstar_pcb_archive_loader.cpp b/pcbnew/pcb_io/cadstar/cadstar_pcb_archive_loader.cpp
index 9f405a9e70..85b433f9bd 100644
--- a/pcbnew/pcb_io/cadstar/cadstar_pcb_archive_loader.cpp
+++ b/pcbnew/pcb_io/cadstar/cadstar_pcb_archive_loader.cpp
@@ -1024,15 +1024,15 @@ PAD* CADSTAR_PCB_ARCHIVE_LOADER::getKiCadPad( const COMPONENT_PAD& aCadstarPad,
switch( aCadstarPad.Side )
{
case PAD_SIDE::MAXIMUM: //Bottom side
- padLayerSet |= LSET( 3, B_Cu, B_Paste, B_Mask );
+ padLayerSet |= LSET( { B_Cu, B_Paste, B_Mask } );
break;
case PAD_SIDE::MINIMUM: //TOP side
- padLayerSet |= LSET( 3, F_Cu, F_Paste, F_Mask );
+ padLayerSet |= LSET( { F_Cu, F_Paste, F_Mask } );
break;
case PAD_SIDE::THROUGH_HOLE:
- padLayerSet = LSET::AllCuMask() | LSET( 4, F_Mask, B_Mask, F_Paste, B_Paste );
+ padLayerSet = LSET::AllCuMask() | LSET( { F_Mask, B_Mask, F_Paste, B_Paste } );
break;
default:
@@ -1120,7 +1120,7 @@ PAD* CADSTAR_PCB_ARCHIVE_LOADER::getKiCadPad( const COMPONENT_PAD& aCadstarPad,
// prevent DRC errors.
// TODO: This could be a custom padstack, update when KiCad supports padstacks
pad->SetAttribute( PAD_ATTRIB::SMD );
- pad->SetLayerSet( LSET( 1, F_Mask ) );
+ pad->SetLayerSet( LSET( F_Mask ) );
}
// zero sized pads seems to break KiCad so lets make it very small instead
@@ -4162,10 +4162,10 @@ LSET CADSTAR_PCB_ARCHIVE_LOADER::getKiCadLayerSet( const LAYER_ID& aCadstarLayer
switch( layerType )
{
case LAYER_TYPE::ALLDOC:
- return LSET( 4, PCB_LAYER_ID::Dwgs_User,
- PCB_LAYER_ID::Cmts_User,
- PCB_LAYER_ID::Eco1_User,
- PCB_LAYER_ID::Eco2_User )
+ return LSET( { PCB_LAYER_ID::Dwgs_User,
+ PCB_LAYER_ID::Cmts_User,
+ PCB_LAYER_ID::Eco1_User,
+ PCB_LAYER_ID::Eco2_User } )
| LSET::UserDefinedLayers();
case LAYER_TYPE::ALLELEC:
@@ -4173,10 +4173,10 @@ LSET CADSTAR_PCB_ARCHIVE_LOADER::getKiCadLayerSet( const LAYER_ID& aCadstarLayer
case LAYER_TYPE::ALLLAYER:
return LSET::AllCuMask( m_numCopperLayers )
- | LSET( 4, PCB_LAYER_ID::Dwgs_User,
- PCB_LAYER_ID::Cmts_User,
- PCB_LAYER_ID::Eco1_User,
- PCB_LAYER_ID::Eco2_User )
+ | LSET( { PCB_LAYER_ID::Dwgs_User,
+ PCB_LAYER_ID::Cmts_User,
+ PCB_LAYER_ID::Eco1_User,
+ PCB_LAYER_ID::Eco2_User } )
| LSET::UserDefinedLayers()
| LSET::AllBoardTechMask();
diff --git a/pcbnew/pcb_io/eagle/pcb_io_eagle.cpp b/pcbnew/pcb_io/eagle/pcb_io_eagle.cpp
index 4e6b8de55c..e0acf4b9ea 100644
--- a/pcbnew/pcb_io/eagle/pcb_io_eagle.cpp
+++ b/pcbnew/pcb_io/eagle/pcb_io_eagle.cpp
@@ -2487,8 +2487,8 @@ void PCB_IO_EAGLE::packageSMD( FOOTPRINT* aFootprint, wxXmlNode* aTree ) const
pad->SetSize( padSize );
pad->SetLayer( layer );
- const LSET front( 3, F_Cu, F_Paste, F_Mask );
- const LSET back( 3, B_Cu, B_Paste, B_Mask );
+ const LSET front( { F_Cu, F_Paste, F_Mask } );
+ const LSET back( { B_Cu, B_Paste, B_Mask } );
if( layer == F_Cu )
pad->SetLayerSet( front );
@@ -2995,7 +2995,7 @@ std::tuple<PCB_LAYER_ID, LSET, bool> PCB_IO_EAGLE::defaultKicadLayer( int aEagle
case EAGLE_LAYER::DIMENSION:
kiLayer = Edge_Cuts;
required = true;
- permittedLayers = LSET( 1, Edge_Cuts );
+ permittedLayers = LSET( Edge_Cuts );
break;
case EAGLE_LAYER::TPLACE:
diff --git a/pcbnew/pcb_io/easyeda/pcb_io_easyeda_parser.cpp b/pcbnew/pcb_io/easyeda/pcb_io_easyeda_parser.cpp
index 430ae31dbf..efcc9a68db 100644
--- a/pcbnew/pcb_io/easyeda/pcb_io_easyeda_parser.cpp
+++ b/pcbnew/pcb_io/easyeda/pcb_io_easyeda_parser.cpp
@@ -984,7 +984,7 @@ void PCB_IO_EASYEDA_PARSER::ParseToBoardItemContainer(
else
{
pad->SetLayer( klayer );
- pad->SetLayerSet( LSET( 1, klayer ) );
+ pad->SetLayerSet( LSET( klayer ) );
pad->SetAttribute( PAD_ATTRIB::SMD );
}
diff --git a/pcbnew/pcb_io/geda/pcb_io_geda.cpp b/pcbnew/pcb_io/geda/pcb_io_geda.cpp
index a8d2d9ba1c..714df8dfad 100644
--- a/pcbnew/pcb_io/geda/pcb_io_geda.cpp
+++ b/pcbnew/pcb_io/geda/pcb_io_geda.cpp
@@ -508,8 +508,8 @@ FOOTPRINT* GPCB_FPL_CACHE::parseFOOTPRINT( LINE_READER* aLineReader )
std::unique_ptr<PAD> pad = std::make_unique<PAD>( footprint.get() );
- static const LSET pad_front( 3, F_Cu, F_Mask, F_Paste );
- static const LSET pad_back( 3, B_Cu, B_Mask, B_Paste );
+ static const LSET pad_front( { F_Cu, F_Mask, F_Paste } );
+ static const LSET pad_back( { B_Cu, B_Mask, B_Paste } );
pad->SetShape( PAD_SHAPE::RECTANGLE );
pad->SetAttribute( PAD_ATTRIB::SMD );
@@ -604,7 +604,7 @@ FOOTPRINT* GPCB_FPL_CACHE::parseFOOTPRINT( LINE_READER* aLineReader )
pad->SetShape( PAD_SHAPE::CIRCLE );
- static const LSET pad_set = LSET::AllCuMask() | LSET( 3, F_SilkS, F_Mask, B_Mask );
+ static const LSET pad_set = LSET::AllCuMask() | LSET( { F_SilkS, F_Mask, B_Mask } );
pad->SetLayerSet( pad_set );
diff --git a/pcbnew/pcb_io/ipc2581/pcb_io_ipc2581.cpp b/pcbnew/pcb_io/ipc2581/pcb_io_ipc2581.cpp
index 0c36813152..b017be518d 100644
--- a/pcbnew/pcb_io/ipc2581/pcb_io_ipc2581.cpp
+++ b/pcbnew/pcb_io/ipc2581/pcb_io_ipc2581.cpp
@@ -755,10 +755,10 @@ void PCB_IO_IPC2581::addShape( wxXmlNode* aContentNode, const PAD& aPad, PCB_LAY
wxString name;
VECTOR2I expansion{ 0, 0 };
- if( LSET( 2, F_Mask, B_Mask ).Contains( aLayer ) )
+ if( LSET( { F_Mask, B_Mask } ).Contains( aLayer ) )
expansion.x = expansion.y = 2 * aPad.GetSolderMaskExpansion();
- if( LSET( 2, F_Paste, B_Paste ).Contains( aLayer ) )
+ if( LSET( { F_Paste, B_Paste } ).Contains( aLayer ) )
expansion = 2 * aPad.GetSolderPasteMargin();
switch( aPad.GetShape() )
diff --git a/pcbnew/pcb_io/kicad_sexpr/pcb_io_kicad_sexpr.cpp b/pcbnew/pcb_io/kicad_sexpr/pcb_io_kicad_sexpr.cpp
index 679ce3a50c..64f38714f5 100644
--- a/pcbnew/pcb_io/kicad_sexpr/pcb_io_kicad_sexpr.cpp
+++ b/pcbnew/pcb_io/kicad_sexpr/pcb_io_kicad_sexpr.cpp
@@ -1392,13 +1392,13 @@ void PCB_IO_KICAD_SEXPR::formatLayers( LSET aLayerMask, int aNestLevel ) const
output += "(layers";
static const LSET cu_all( LSET::AllCuMask() );
- static const LSET fr_bk( 2, B_Cu, F_Cu );
- static const LSET adhes( 2, B_Adhes, F_Adhes );
- static const LSET paste( 2, B_Paste, F_Paste );
- static const LSET silks( 2, B_SilkS, F_SilkS );
- static const LSET mask( 2, B_Mask, F_Mask );
- static const LSET crt_yd( 2, B_CrtYd, F_CrtYd );
- static const LSET fab( 2, B_Fab, F_Fab );
+ static const LSET fr_bk( { B_Cu, F_Cu } );
+ static const LSET adhes( { B_Adhes, F_Adhes } );
+ static const LSET paste( { B_Paste, F_Paste } );
+ static const LSET silks( { B_SilkS, F_SilkS } );
+ static const LSET mask( { B_Mask, F_Mask } );
+ static const LSET crt_yd( { B_CrtYd, F_CrtYd } );
+ static const LSET fab( { B_Fab, F_Fab } );
LSET cu_mask = cu_all;
diff --git a/pcbnew/pcb_io/kicad_sexpr/pcb_io_kicad_sexpr.h b/pcbnew/pcb_io/kicad_sexpr/pcb_io_kicad_sexpr.h
index ccbc26bcc7..d81e0e578a 100644
--- a/pcbnew/pcb_io/kicad_sexpr/pcb_io_kicad_sexpr.h
+++ b/pcbnew/pcb_io/kicad_sexpr/pcb_io_kicad_sexpr.h
@@ -31,7 +31,6 @@
#include <richio.h>
#include <string>
#include <layer_ids.h>
-#include <lset.h>
#include <boost/ptr_container/ptr_map.hpp>
#include <wx_filename.h>
#include "widgets/report_severity.h"
@@ -42,6 +41,7 @@ class FP_CACHE;
class PCB_IO_KICAD_SEXPR_PARSER;
class NETINFO_MAPPING;
class BOARD_DESIGN_SETTINGS;
+class LSET;
class PCB_DIMENSION_BASE;
class PCB_SHAPE;
class PCB_REFERENCE_IMAGE;
diff --git a/pcbnew/pcb_io/kicad_sexpr/pcb_io_kicad_sexpr_parser.cpp b/pcbnew/pcb_io/kicad_sexpr/pcb_io_kicad_sexpr_parser.cpp
index b54a1727e4..8835147b1f 100644
--- a/pcbnew/pcb_io/kicad_sexpr/pcb_io_kicad_sexpr_parser.cpp
+++ b/pcbnew/pcb_io/kicad_sexpr/pcb_io_kicad_sexpr_parser.cpp
@@ -109,13 +109,13 @@ void PCB_IO_KICAD_SEXPR_PARSER::init()
m_layerMasks[ "*.Cu" ] = LSET::AllCuMask();
m_layerMasks[ "*In.Cu" ] = LSET::InternalCuMask();
- m_layerMasks[ "F&B.Cu" ] = LSET( 2, F_Cu, B_Cu );
- m_layerMasks[ "*.Adhes" ] = LSET( 2, B_Adhes, F_Adhes );
- m_layerMasks[ "*.Paste" ] = LSET( 2, B_Paste, F_Paste );
- m_layerMasks[ "*.Mask" ] = LSET( 2, B_Mask, F_Mask );
- m_layerMasks[ "*.SilkS" ] = LSET( 2, B_SilkS, F_SilkS );
- m_layerMasks[ "*.Fab" ] = LSET( 2, B_Fab, F_Fab );
- m_layerMasks[ "*.CrtYd" ] = LSET( 2, B_CrtYd, F_CrtYd );
+ m_layerMasks[ "F&B.Cu" ] = LSET( { F_Cu, B_Cu } );
+ m_layerMasks[ "*.Adhes" ] = LSET( { B_Adhes, F_Adhes } );
+ m_layerMasks[ "*.Paste" ] = LSET( { B_Paste, F_Paste } );
+ m_layerMasks[ "*.Mask" ] = LSET( { B_Mask, F_Mask } );
+ m_layerMasks[ "*.SilkS" ] = LSET( { B_SilkS, F_SilkS } );
+ m_layerMasks[ "*.Fab" ] = LSET( { B_Fab, F_Fab } );
+ m_layerMasks[ "*.CrtYd" ] = LSET( { B_CrtYd, F_CrtYd } );
// This is for the first pretty & *.kicad_pcb formats, which had
// Inner1_Cu - Inner14_Cu with the numbering sequence
diff --git a/pcbnew/pcb_io/pcad/pcad_pad.cpp b/pcbnew/pcb_io/pcad/pcad_pad.cpp
index a7fb8d3850..4fab67d569 100644
--- a/pcbnew/pcb_io/pcad/pcad_pad.cpp
+++ b/pcbnew/pcb_io/pcad/pcad_pad.cpp
@@ -222,7 +222,7 @@ void PCAD_PAD::AddToFootprint( FOOTPRINT* aFootprint, const EDA_ANGLE& aRotation
pad->SetLocalClearance( sm_margin + pcbIUScale.mmToIU( 0.254 ) );
}
- pad->SetLayerSet( LSET::AllCuMask() | LSET( 2, B_Mask, F_Mask ) );
+ pad->SetLayerSet( LSET::AllCuMask() | LSET( { B_Mask, F_Mask } ) );
}
else
{
@@ -244,9 +244,9 @@ void PCAD_PAD::AddToFootprint( FOOTPRINT* aFootprint, const EDA_ANGLE& aRotation
// assume this is SMD pad
if( padShape->m_KiCadLayer == F_Cu )
- pad->SetLayerSet( LSET( 3, F_Cu, F_Paste, F_Mask ) );
+ pad->SetLayerSet( LSET( { F_Cu, F_Paste, F_Mask } ) );
else
- pad->SetLayerSet( LSET( 3, B_Cu, B_Paste, B_Mask ) );
+ pad->SetLayerSet( LSET( { B_Cu, B_Paste, B_Mask } ) );
break;
}
@@ -261,7 +261,7 @@ void PCAD_PAD::AddToFootprint( FOOTPRINT* aFootprint, const EDA_ANGLE& aRotation
if( padType == PAD_ATTRIB::PTH )
// actually this is a thru-hole pad
- pad->SetLayerSet( LSET::AllCuMask() | LSET( 2, B_Mask, F_Mask ) );
+ pad->SetLayerSet( LSET::AllCuMask() | LSET( { B_Mask, F_Mask } ) );
pad->SetNumber( m_Name.text );
diff --git a/pcbnew/pcb_plot_params.cpp b/pcbnew/pcb_plot_params.cpp
index a3432d0e2d..5100242069 100644
--- a/pcbnew/pcb_plot_params.cpp
+++ b/pcbnew/pcb_plot_params.cpp
@@ -131,8 +131,8 @@ PCB_PLOT_PARAMS::PCB_PLOT_PARAMS()
m_widthAdjust = 0.;
m_textMode = PLOT_TEXT_MODE::DEFAULT;
m_outputDirectory.clear();
- m_layerSelection = LSET( 7, F_SilkS, B_SilkS, F_Mask, B_Mask,
- F_Paste, B_Paste, Edge_Cuts )
+ m_layerSelection = LSET( { F_SilkS, B_SilkS, F_Mask, B_Mask,
+ F_Paste, B_Paste, Edge_Cuts } )
| LSET::AllCuMask();
m_PDFFrontFPPropertyPopups = true;
@@ -455,7 +455,7 @@ void PCB_PLOT_PARAMS_PARSER::Parse( PCB_PLOT_PARAMS* aPcbPlotParams )
// number without knowing the number or total Cu layers in the legacy board.
// We do not have that information here, so simply set all layers ON. User
// can turn them off in the UI.
- aPcbPlotParams->m_layerSelection = LSET( 2, F_SilkS, B_SilkS ) | LSET::AllCuMask();
+ aPcbPlotParams->m_layerSelection = LSET( { F_SilkS, B_SilkS } ) | LSET::AllCuMask();
}
else if( cur.find_first_of( "0x" ) == 0 ) // pretty ver. 4.
{
diff --git a/pcbnew/plot_board_layers.cpp b/pcbnew/plot_board_layers.cpp
index 34bf34430d..998fae389c 100644
--- a/pcbnew/plot_board_layers.cpp
+++ b/pcbnew/plot_board_layers.cpp
@@ -287,8 +287,8 @@ void PlotStandardLayer( BOARD* aBoard, PLOTTER* aPlotter, LSET aLayerMask,
OUTLINE_MODE plotMode = aPlotOpt.GetPlotMode();
bool onCopperLayer = ( LSET::AllCuMask() & aLayerMask ).any();
- bool onSolderMaskLayer = ( LSET( 2, F_Mask, B_Mask ) & aLayerMask ).any();
- bool onSolderPasteLayer = ( LSET( 2, F_Paste, B_Paste ) & aLayerMask ).any();
+ bool onSolderMaskLayer = ( LSET( { F_Mask, B_Mask } ) & aLayerMask ).any();
+ bool onSolderPasteLayer = ( LSET( { F_Paste, B_Paste } ) & aLayerMask ).any();
bool onFrontFab = ( LSET( F_Fab ) & aLayerMask ).any();
bool onBackFab = ( LSET( B_Fab ) & aLayerMask ).any();
bool sketchPads = ( onFrontFab || onBackFab ) && aPlotOpt.GetSketchPadsOnFabLayers();
diff --git a/pcbnew/plotcontroller.h b/pcbnew/plotcontroller.h
index 51e06fbba8..5092db1a6e 100644
--- a/pcbnew/plotcontroller.h
+++ b/pcbnew/plotcontroller.h
@@ -32,10 +32,10 @@
#include <pcb_plot_params.h>
#include <layer_ids.h>
-#include <lset.h>
class PLOTTER;
class BOARD;
+class LSEQ;
/**
diff --git a/pcbnew/tools/pcb_grid_helper.h b/pcbnew/tools/pcb_grid_helper.h
index 64ef88f81a..046a7adfc9 100644
--- a/pcbnew/tools/pcb_grid_helper.h
+++ b/pcbnew/tools/pcb_grid_helper.h
@@ -28,10 +28,10 @@
#include <vector>
-#include <lset.h>
#include <pcb_item_containers.h>
#include <tool/grid_helper.h>
+class LSET;
class SHAPE_ARC;
class TOOL_MANAGER;
struct MAGNETIC_SETTINGS;
diff --git a/pcbnew/tools/pcb_selection_tool.cpp b/pcbnew/tools/pcb_selection_tool.cpp
index 723214e223..78a241e315 100644
--- a/pcbnew/tools/pcb_selection_tool.cpp
+++ b/pcbnew/tools/pcb_selection_tool.cpp
@@ -3463,8 +3463,8 @@ void PCB_SELECTION_TOOL::pruneObscuredSelectionCandidates( GENERAL_COLLECTOR& aC
void PCB_SELECTION_TOOL::GuessSelectionCandidates( GENERAL_COLLECTOR& aCollector,
const VECTOR2I& aWhere ) const
{
- static const LSET silkLayers( 2, B_SilkS, F_SilkS );
- static const LSET courtyardLayers( 2, B_CrtYd, F_CrtYd );
+ static const LSET silkLayers( { B_SilkS, F_SilkS } );
+ static const LSET courtyardLayers( { B_CrtYd, F_CrtYd } );
static std::vector<KICAD_T> singleLayerSilkTypes = { PCB_FIELD_T,
PCB_TEXT_T, PCB_TEXTBOX_T,
PCB_TABLE_T, PCB_TABLECELL_T,
diff --git a/qa/tests/pcbnew/test_lset.cpp b/qa/tests/pcbnew/test_lset.cpp
index 2d95415df1..4b7a713b99 100644
--- a/qa/tests/pcbnew/test_lset.cpp
+++ b/qa/tests/pcbnew/test_lset.cpp
@@ -39,9 +39,9 @@ struct LSETS_TO_TEST
const static std::vector<LSETS_TO_TEST> type_to_ext_cases = {
- { LSET( 2, F_Cu, F_Fab ), "0020000_00000001",
+ { LSET( { F_Cu, F_Fab } ), "0020000_00000001",
"0000|0000_0010|0000_0000|0000_0000|0000_0000|0000_0000|0000_0000|0000_0001" },
- { LSET( 3, In14_Cu, B_Adhes, Rescue ), "8000001_00004000",
+ { LSET( { In14_Cu, B_Adhes, Rescue } ), "8000001_00004000",
"1000|0000_0000|0000_0000|0000_0001|0000_0000|0000_0000|0100_0000|0000_0000" }
};