mirror of
https://gitlab.com/kicad/code/kicad.git
synced 2024-11-22 11:35:00 +00:00
336 lines
12 KiB
C++
336 lines
12 KiB
C++
/*
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* This program source code file is part of KiCad, a free EDA CAD application.
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*
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* Copyright (C) 2004-2022 KiCad Developers.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, you may find one here:
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* http://www.gnu.org/licenses/old-licenses/gpl-2.0.html
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* or you may search the http://www.gnu.org website for the version 2 license,
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* or you may write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
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*/
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#include <board.h>
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#include <pad.h>
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#include <drc/drc_engine.h>
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#include <drc/drc_item.h>
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#include <drc/drc_rule.h>
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#include <drc/drc_test_provider.h>
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#include <kiway.h>
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#include <netlist_reader/pcb_netlist.h>
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/*
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Schematic parity test.
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Errors generated:
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- DRCE_MISSING_FOOTPRINT
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- DRCE_DUPLICATE_FOOTPRINT
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- DRCE_EXTRA_FOOTPRINT
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- DRCE_SCHEMATIC_PARITY
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- DRCE_FOOTPRINT_FILTERS
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TODO:
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- cross-check PCB netlist against SCH netlist
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- cross-check PCB fields against SCH fields
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*/
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class DRC_TEST_PROVIDER_SCHEMATIC_PARITY : public DRC_TEST_PROVIDER
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{
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public:
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DRC_TEST_PROVIDER_SCHEMATIC_PARITY()
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{
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m_isRuleDriven = false;
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}
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virtual ~DRC_TEST_PROVIDER_SCHEMATIC_PARITY()
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{
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}
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virtual bool Run() override;
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virtual const wxString GetName() const override
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{
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return wxT( "schematic_parity" );
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};
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virtual const wxString GetDescription() const override
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{
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return wxT( "Performs layout-vs-schematics integity check" );
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}
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private:
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void testNetlist( NETLIST& aNetlist );
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};
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void DRC_TEST_PROVIDER_SCHEMATIC_PARITY::testNetlist( NETLIST& aNetlist )
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{
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BOARD* board = m_drcEngine->GetBoard();
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auto compare = []( const FOOTPRINT* x, const FOOTPRINT* y )
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{
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return x->GetReference().CmpNoCase( y->GetReference() ) < 0;
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};
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auto footprints = std::set<FOOTPRINT*, decltype( compare )>( compare );
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// Search for duplicate footprints on the board
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for( FOOTPRINT* footprint : board->Footprints() )
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{
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if( m_drcEngine->IsErrorLimitExceeded( DRCE_DUPLICATE_FOOTPRINT ) )
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break;
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auto ins = footprints.insert( footprint );
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if( !ins.second && !( footprint->GetAttributes() & FP_BOARD_ONLY ) )
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{
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std::shared_ptr<DRC_ITEM> drcItem = DRC_ITEM::Create( DRCE_DUPLICATE_FOOTPRINT );
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drcItem->SetItems( footprint, *ins.first );
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reportViolation( drcItem, footprint->GetPosition(), UNDEFINED_LAYER );
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}
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}
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// Search for component footprints in the netlist but not on the board.
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for( unsigned ii = 0; ii < aNetlist.GetCount(); ii++ )
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{
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COMPONENT* component = aNetlist.GetComponent( ii );
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FOOTPRINT* footprint = board->FindFootprintByReference( component->GetReference() );
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if( footprint == nullptr )
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{
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if( !m_drcEngine->IsErrorLimitExceeded( DRCE_MISSING_FOOTPRINT ) )
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{
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wxString msg;
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msg.Printf( _( "Missing footprint %s (%s)" ),
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component->GetReference(),
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component->GetValue() );
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std::shared_ptr<DRC_ITEM> drcItem = DRC_ITEM::Create( DRCE_MISSING_FOOTPRINT );
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drcItem->SetErrorMessage( msg );
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reportViolation( drcItem, VECTOR2I(), UNDEFINED_LAYER );
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}
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}
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else
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{
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if( component->GetValue() != footprint->GetValue()
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&& !m_drcEngine->IsErrorLimitExceeded( DRCE_SCHEMATIC_PARITY ) )
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{
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wxString msg;
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msg.Printf( _( "Value (%s) doesn't match symbol value (%s)." ),
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footprint->GetReference(), footprint->GetValue(),
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component->GetValue() );
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std::shared_ptr<DRC_ITEM> drcItem = DRC_ITEM::Create( DRCE_SCHEMATIC_PARITY );
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drcItem->SetErrorMessage( msg );
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drcItem->SetItems( footprint );
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reportViolation( drcItem, footprint->GetPosition(), UNDEFINED_LAYER );
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}
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if( component->GetFPID().GetUniStringLibId() != footprint->GetFPID().GetUniStringLibId()
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&& !m_drcEngine->IsErrorLimitExceeded( DRCE_SCHEMATIC_PARITY ) )
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{
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wxString msg;
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msg.Printf( _( "%s doesn't match footprint given by symbol (%s)." ),
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footprint->GetFPID().GetUniStringLibId(),
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component->GetFPID().GetUniStringLibId() );
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std::shared_ptr<DRC_ITEM> drcItem = DRC_ITEM::Create( DRCE_SCHEMATIC_PARITY );
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drcItem->SetErrorMessage( msg );
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drcItem->SetItems( footprint );
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reportViolation( drcItem, footprint->GetPosition(), UNDEFINED_LAYER );
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}
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if( !m_drcEngine->IsErrorLimitExceeded( DRCE_FOOTPRINT_FILTERS ) )
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{
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wxString fpName = footprint->GetFPID().GetUniStringLibItemName();
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size_t filtercount = component->GetFootprintFilters().GetCount();
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bool found = ( 0 == filtercount ); // if no entries, do not filter
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for( size_t jj = 0; jj < filtercount && !found; jj++ )
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found = fpName.Matches( component->GetFootprintFilters()[jj] );
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if( !found )
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{
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wxString msg;
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msg.Printf( _( "%s doesn't match symbol's footprint filters (%s)." ),
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fpName,
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wxJoin( component->GetFootprintFilters(), ' ' ) );
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std::shared_ptr<DRC_ITEM> drcItem = DRC_ITEM::Create( DRCE_FOOTPRINT_FILTERS );
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drcItem->SetErrorMessage( msg );
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drcItem->SetItems( footprint );
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reportViolation( drcItem, footprint->GetPosition(), UNDEFINED_LAYER );
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}
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}
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if( ( component->GetProperties().count( "dnp" ) > 0 )
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!= ( ( footprint->GetAttributes() & FP_DNP ) > 0 )
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&& !m_drcEngine->IsErrorLimitExceeded( DRCE_SCHEMATIC_PARITY ) )
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{
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wxString msg;
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msg.Printf( _( "'%s' settings differ." ), _( "Do not populate" ) );
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std::shared_ptr<DRC_ITEM> drcItem = DRC_ITEM::Create( DRCE_SCHEMATIC_PARITY );
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drcItem->SetErrorMessage( drcItem->GetErrorMessage() + wxS( ": " ) + msg );
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drcItem->SetItems( footprint );
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reportViolation( drcItem, footprint->GetPosition(), UNDEFINED_LAYER );
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}
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if( ( component->GetProperties().count( "exclude_from_bom" ) > 0 )
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!= ( (footprint->GetAttributes() & FP_EXCLUDE_FROM_BOM ) > 0 )
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&& !m_drcEngine->IsErrorLimitExceeded( DRCE_SCHEMATIC_PARITY ) )
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{
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wxString msg;
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msg.Printf( _( "'%s' settings differ." ), _( "Exclude from bill of materials" ) );
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std::shared_ptr<DRC_ITEM> drcItem = DRC_ITEM::Create( DRCE_SCHEMATIC_PARITY );
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drcItem->SetErrorMessage( drcItem->GetErrorMessage() + wxS( ": " ) + msg );
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drcItem->SetItems( footprint );
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reportViolation( drcItem, footprint->GetPosition(), UNDEFINED_LAYER );
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}
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for( PAD* pad : footprint->Pads() )
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{
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if( m_drcEngine->IsErrorLimitExceeded( DRCE_NET_CONFLICT ) )
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break;
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if( !pad->CanHaveNumber() )
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continue;
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const COMPONENT_NET& sch_net = component->GetNet( pad->GetNumber() );
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const wxString& pcb_netname = pad->GetNetname();
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if( !pcb_netname.IsEmpty() && sch_net.GetPinName().IsEmpty() )
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{
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wxString msg;
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msg.Printf( _( "No corresponding pin found in schematic." ) );
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std::shared_ptr<DRC_ITEM> drcItem = DRC_ITEM::Create( DRCE_NET_CONFLICT );
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drcItem->SetErrorMessage( msg );
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drcItem->SetItems( pad );
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reportViolation( drcItem, footprint->GetPosition(), UNDEFINED_LAYER );
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}
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else if( pcb_netname.IsEmpty() && !sch_net.GetNetName().IsEmpty() )
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{
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wxString msg;
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msg.Printf( _( "Pad missing net given by schematic (%s)." ),
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sch_net.GetNetName() );
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std::shared_ptr<DRC_ITEM> drcItem = DRC_ITEM::Create( DRCE_NET_CONFLICT );
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drcItem->SetErrorMessage( msg );
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drcItem->SetItems( pad );
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reportViolation( drcItem, footprint->GetPosition(), UNDEFINED_LAYER );
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}
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else if( pcb_netname != sch_net.GetNetName()
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&& !( pcb_netname.starts_with(
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wxT( "unconnected-" ) )
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&& pcb_netname.starts_with( sch_net.GetNetName() ) ) )
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{
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wxString msg;
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msg.Printf( _( "Pad net (%s) doesn't match net given by schematic (%s)." ),
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pcb_netname,
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sch_net.GetNetName() );
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std::shared_ptr<DRC_ITEM> drcItem = DRC_ITEM::Create( DRCE_NET_CONFLICT );
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drcItem->SetErrorMessage( msg );
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drcItem->SetItems( pad );
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reportViolation( drcItem, footprint->GetPosition(), UNDEFINED_LAYER );
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}
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}
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for( unsigned jj = 0; jj < component->GetNetCount(); ++jj )
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{
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if( m_drcEngine->IsErrorLimitExceeded( DRCE_NET_CONFLICT ) )
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break;
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const COMPONENT_NET& sch_net = component->GetNet( jj );
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if( !footprint->FindPadByNumber( sch_net.GetPinName() ) )
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{
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wxString msg;
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if( sch_net.GetNetName().StartsWith( wxT( "unconnected-" ) ) )
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{
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msg = sch_net.GetPinName();
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}
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else
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{
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msg = wxString::Format( wxT( "%s (%s)" ),
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sch_net.GetPinName(),
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sch_net.GetNetName() );
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}
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msg.Printf( _( "No pad found for pin %s in schematic." ), msg );
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std::shared_ptr<DRC_ITEM> drcItem = DRC_ITEM::Create( DRCE_NET_CONFLICT );
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drcItem->SetErrorMessage( msg );
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drcItem->SetItems( footprint );
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reportViolation( drcItem, footprint->GetPosition(), UNDEFINED_LAYER );
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}
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}
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}
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}
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// Search for component footprints found on board but not in netlist.
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for( FOOTPRINT* footprint : board->Footprints() )
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{
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if( m_drcEngine->IsErrorLimitExceeded( DRCE_EXTRA_FOOTPRINT ) )
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break;
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if( footprint->GetAttributes() & FP_BOARD_ONLY )
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continue;
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if( !aNetlist.GetComponentByReference( footprint->GetReference() ) )
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{
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std::shared_ptr<DRC_ITEM> drcItem = DRC_ITEM::Create( DRCE_EXTRA_FOOTPRINT );
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drcItem->SetItems( footprint );
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reportViolation( drcItem, footprint->GetPosition(), UNDEFINED_LAYER );
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}
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}
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}
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bool DRC_TEST_PROVIDER_SCHEMATIC_PARITY::Run()
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{
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if( m_drcEngine->GetTestFootprints() )
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{
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if( !reportPhase( _( "Checking PCB to schematic parity..." ) ) )
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return false;
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auto netlist = m_drcEngine->GetSchematicNetlist();
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if( !netlist )
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{
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reportAux( wxT( "No netlist provided, skipping schematic parity tests." ) );
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return true;
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}
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testNetlist( *netlist );
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reportRuleStatistics();
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}
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return !m_drcEngine->IsCancelled();
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}
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namespace detail
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{
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static DRC_REGISTER_TEST_PROVIDER<DRC_TEST_PROVIDER_SCHEMATIC_PARITY> dummy;
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}
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