mirror of
https://gitlab.com/kicad/code/kicad.git
synced 2024-11-22 17:35:24 +00:00
68 lines
1.2 KiB
INI
68 lines
1.2 KiB
INI
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ViaDiameter=0.889
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ViaDrill=0.4
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uViaDiameter=0.508
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uViaDrill=0.127
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dPairWidth=0.2
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dPairGap=0.25
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dPairViaGap=0.25
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update=Thu 21 May 2020 16:15:39 EDT
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last_client=eeschema
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[pcbnew/Netclasses/1]
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Name=pwr
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Clearance=0.2
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TrackWidth=0.23
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ViaDiameter=0.889
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ViaDrill=0.4
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uViaDiameter=0.508
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uViaDrill=0.127
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dPairWidth=0.2
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dPairGap=0.25
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dPairViaGap=0.25
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[sheetnames]
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1=84d4d60f-6656-461e-b8d6-5d42ccee0251:
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2=00000000-0000-0000-0000-00004bf03687:buspci.sch
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3=00000000-0000-0000-0000-00004bf03683:graphic
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4=00000000-0000-0000-0000-00004bf03689:ESVIDEO-RVB
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5=00000000-0000-0000-0000-00004bf03681:pal-ntsc.sch
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6=00000000-0000-0000-0000-00004bf03685:RAMS
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7=00000000-0000-0000-0000-00004bf0367d:muxdata
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8=00000000-0000-0000-0000-00004bf0367f:modul
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[schematic_editor]
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version=1
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PageLayoutDescrFile=
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PlotDirectoryName=
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NetFmtName=Pcbnew
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SpiceAjustPassiveValues=0
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SubpartIdSeparator=0
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SubpartFirstId=65
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LabSize=50
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TextOffsetRatio=0.3
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LineThickness=6
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BusThickness=12
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WireThickness=6
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PinSymbolSize=25
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JunctionSize=40
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FieldNameTemplates=(templatefields)
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ERC_TestSimilarLabels=1
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ERC_CheckUniqueGlobalLabels=1
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ERC_CheckBusDriverConflicts=1
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ERC_CheckBusEntryConflicts=1
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ERC_CheckBusToBusConflicts=1
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ERC_CheckBusToNetConflicts=1
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