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49 lines
1.5 KiB
Plaintext
49 lines
1.5 KiB
Plaintext
RF layer1, layer 2 GND
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thickness of roger determines line width
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ground must be continuous under RF traces, keep away from RF
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flood 5V power on layer 3
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routing on layer 3 and layer 4
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ground on same layer as RF needs to 2x dialelectric thickness(distance between RF and GND) away. Try for >30 mils
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Questions:
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Special considerations for power/ground pins on RF ICs?
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3.3V power plane would remove a bunch of resistors
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component pads centered on RF trace?
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Sunstone annular ring size
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GND pads within keepout, should I use a long GND trace or a close via?
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different switch and header footprint?
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no solder mask on traces
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RF trace adjacent vias in pads
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more caps on the SMPS?
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power select header needs another position for lab supply in?
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Do high power ground header pins need thermals?
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Do I need thermals on ground plane?
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Add an extra test for how traces are necked into pads?
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update PSAS logo with silk circle
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TO-DO
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DONE Power Divider resistor
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DONE change ref des on SMPS to original
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approved DRC errors
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smaller vias!
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NEW TODO:
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DONE Window tCream
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DONE number header
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NEWER TODO:
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DONE Label LEDs
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DONE move vias out of stub keepout
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DONE breakoff holes aligned with edge
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DONE fix tDoc on logic section
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DONE change traces on logic to .2 and use bottom layer
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DONE pull in vias around caps on boost converter and check for small clearances
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DONE make tCream bigger on PA.
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DONE Move vias out of tStop on PA footprint
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DONE change width of tStop on RF traces
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DONE via spacing at 1.5mm to let 5v through
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FINAL
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What should I call the wifi card side, HOST?
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