Updated stencil for paste layer to include Pico for Macrofab manufacturing. Updated layout / sch to match.

2025-04-22 11:43:43 +00:00 · 2023-12-27 19:51:41 -05:00 · 2023-12-27 19:51:41 -05:00 · 277a5df9ec
commit 277a5df9ec
parent c0e717195d
7 changed files with 387 additions and 91200 deletions
--- a/bom.ini
+++ b/bom.ini
@ -0,0 +1,118 @@
+[BOM_OPTIONS]
+; General BoM options here
+; If 'ignore_dnf' option is set to 1, rows that are not to be fitted on the PCB will not be written to the BoM file
+ignore_dnf = 1
+; If 'html_generate_dnf' option is set to 1, also generate a list of components not fitted on the PCB (HTML only)
+html_generate_dnf = 1
+; If 'use_alt' option is set to 1, grouped references will be printed in the alternate compressed style eg: R1-R7,R18
+use_alt = 0
+; If 'number_rows' option is set to 1, each row in the BoM will be prepended with an incrementing row number
+number_rows = 1
+; If 'group_connectors' option is set to 1, connectors with the same footprints will be grouped together, independent of the name of the connector
+group_connectors = 1
+; If 'test_regex' option is set to 1, each component group will be tested against a number of regular-expressions (specified, per column, below). If any matches are found, the row is ignored in the output file
+test_regex = 1
+; If 'merge_blank_fields' option is set to 1, component groups with blank fields will be merged into the most compatible group, where possible
+merge_blank_fields = 1
+; Specify output file name format, %O is the defined output name, %v is the version, %V is the variant name which will be ammended according to 'variant_file_name_format'.
+output_file_name = %O_bom_%v%V
+; Specify the variant file name format, this is a unique field as the variant is not always used/specified. When it is unused you will want to strip all of this.
+variant_file_name_format = _(%V)
+; Field name used to determine if a particular part is to be fitted
+fit_field = Population
+; Complex variant processing (disabled by default)
+complex_variant = False
+; Character used to separate reference designators in output
+ref_separator = ' '
+; Make a backup of the bom before generating the new one, using the following template
+make_backup = %O.tmp
+; Put the datasheet as a link for the following field
+datasheet_as_link = False
+; Default number of boards to produce if none given on CLI with -n
+number_boards = 1
+; Default PCB variant if none given on CLI with -r
+board_variant = ['default']
+; Whether to hide headers from output file
+hide_headers = False
+; Whether to hide PCB info from output file
+hide_pcb_info = False
+; Interpret as a Digikey P/N and link the following field
+digikey_link = False
+; Interpret as a MOUSER P/N and link the following field
+mouser_link = False
+
+[IGNORE_COLUMNS]
+; Any column heading that appears here will be excluded from the Generated BoM
+; Titles are case-insensitive
+part lib
+footprint lib
+sheetpath
+
+[COLUMN_ORDER]
+; Columns will apear in the order they are listed here
+; Titles are case-insensitive
+References
+Value
+MPN1
+Vendor1
+;Footprint
+Quantity Per PCB
+Link1
+Voltage
+Current
+Footprint
+Population
+
+[GROUP_FIELDS]
+; List of fields used for sorting individual components into groups
+; Components which match (comparing *all* fields) will be grouped together
+; Field names are case-insensitive
+;Part
+;Part Lib
+;Value
+;Footprint
+;Footprint Lib
+;
+[COMPONENT_ALIASES]
+; A series of values which are considered to be equivalent for the part name
+; Each line represents a list of equivalent component name values separated by a tab character
+; e.g. 'c	c_small	cap' will ensure the equivalent capacitor symbols can be grouped together
+; Aliases are case-insensitive
+c	c_small	cap	capacitor
+r	r_small	res	resistor
+sw	switch
+l	l_small	inductor
+zener	zenersmall
+d	diode	d_small
+
+[JOIN]
+; A list of rules to join the content of fields
+; Each line is a rule, the first name is the field that will receive the data
+; from the other fields
+; Use tab (ASCII 9) as separator
+; Field names are case sensitive
+
+[REGEX_INCLUDE]
+; A series of regular expressions used to include parts in the BoM
+; If there are any regex defined here, only components that match against ANY of them will be included in the BOM
+; Column names are case-insensitive
+; Format is: "[ColumName] [Regex]" (separated by a tab)
+
+[COLUMN_RENAME]
+; A list of columns to be renamed
+; Format is: "[ColumName] [NewName]" (separated by a tab)
+
+[REGEX_EXCLUDE]
+; A series of regular expressions used to exclude parts from the BoM
+; If a component matches ANY of these, it will be excluded from the BoM
+; Column names are case-insensitive
+; Format is: "[ColumName] [Regex]" (separated by a tab
+References	^TP[0-9]*
+References	^FID
+Part	mount.*hole
+Part	solder.*bridge
+Part	test.*point
+Footprint	test.*point
+Footprint	mount.*hole
+Footprint	fiducial
+
--- a/91093
+++ b/91093
--- a/ostentus-hw.kicad_pcb
+++ b/ostentus-hw.kicad_pcb
--- a/ostentus-hw.kicad_prl
+++ b/ostentus-hw.kicad_prl
@ -1,6 +1,6 @@
 {
  "board": {
-    "active_layer": 0,
+    "active_layer": 46,
    "active_layer_preset": "",
    "auto_track_width": true,
    "hidden_netclasses": [],
@ -64,7 +64,7 @@
      35,
      36
    ],
-    "visible_layers": "fbfffff_ffffffff",
+    "visible_layers": "fffffff_ffffffff",
    "zone_display_mode": 0
  },
  "meta": {
--- a/ostentus-hw.kicad_pro
+++ b/ostentus-hw.kicad_pro
@ -56,7 +56,15 @@
          "width": 0.0
        }
      ],
-      "drc_exclusions": [],
+      "drc_exclusions": [
+        "malformed_courtyard|185500000|127300000|79e2034e-6053-469c-8434-9bb20d5aa43a|00000000-0000-0000-0000-000000000000",
+        "solder_mask_bridge|132991165|136045674|a35861bc-fc22-42bf-a74d-31d8eaba8382|0413bf8e-797d-41cd-8cc3-55f382a6b062",
+        "solder_mask_bridge|132991263|136047999|a0e29a23-8247-4a04-a44e-3a1580e58245|0413bf8e-797d-41cd-8cc3-55f382a6b062",
+        "solder_mask_bridge|148151293|138092427|d0b24856-5b45-4262-b7ad-9d14bf6f0c18|0f290ae1-4096-43a5-9093-7dbf1a321033",
+        "solder_mask_bridge|149498489|136600212|9a5b1fd5-5357-4903-8665-267fc3a3b67f|0f290ae1-4096-43a5-9093-7dbf1a321033",
+        "solder_mask_bridge|149651290|136592430|d33b20a9-0171-4c8e-b510-abbd7679dcd4|0f290ae1-4096-43a5-9093-7dbf1a321033",
+        "solder_mask_bridge|163176593|135031304|bedc899f-da56-49b2-a462-85dff7f01eea|0840453f-092c-41c1-87a4-a8ffe54c7b0d"
+      ],
      "meta": {
        "version": 2
      },
@ -447,7 +455,7 @@
      "idf": "",
      "netlist": "",
      "specctra_dsn": "",
-      "step": "",
+      "step": "output/mech/ostentus-hw_202312041254.step",
      "vrml": ""
    },
    "page_layout_descr_file": ""
--- a/ostentus-hw.kicad_sch
+++ b/ostentus-hw.kicad_sch
--- a/ostentus.pretty/RPi_Pico_SMD_TH_Paste.kicad_mod
+++ b/ostentus.pretty/RPi_Pico_SMD_TH_Paste.kicad_mod
@ -0,0 +1,123 @@
+(footprint "RPi_Pico_SMD_TH_Paste" (version 20221018) (generator pcbnew)
+  (layer "F.Cu")
+  (descr "Through hole straight pin header, 2x20, 2.54mm pitch, double rows")
+  (tags "Through hole pin header THT 2x20 2.54mm double row")
+  (attr through_hole)
+  (fp_text reference "REF**" (at 0 0 180) (layer "F.SilkS") hide
+      (effects (font (size 1 1) (thickness 0.15)))
+    (tstamp 4db5f045-eaf1-479b-829b-92397ce59e0d)
+  )
+  (fp_text value "RPi_Pico_SMD_TH_Paste" (at 0 2.159 180) (layer "F.Fab")
+      (effects (font (size 1 1) (thickness 0.15)))
+    (tstamp 4727d230-3691-4ec6-a63b-cfb21c9b5402)
+  )
+  (fp_text user "Copper Keepouts shown on Dwgs layer" (at 0.1 -30.2 180) (layer "Cmts.User")
+      (effects (font (size 1 1) (thickness 0.15)))
+    (tstamp e3e40f52-13ea-4aaf-b68d-0f364d7dc3c5)
+  )
+  (fp_text user "${REFERENCE}" (at 0 0 180) (layer "F.Fab")
+      (effects (font (size 1 1) (thickness 0.15)))
+    (tstamp e4c9f54c-ac40-4847-b1fd-a23a0ff3bdc4)
+  )
+  (fp_line (start -10.5 -25.5) (end 10.5 -25.5)
+    (stroke (width 0.12) (type solid)) (layer "F.SilkS") (tstamp 1cfc867a-4662-4391-b129-95dadcda7b88))
+  (fp_line (start -10.5 -22.833) (end -7.493 -22.833)
+    (stroke (width 0.12) (type solid)) (layer "F.SilkS") (tstamp fc8aa8d1-a1a3-45e6-ad26-bcc61794f073))
+  (fp_line (start -7.493 -22.833) (end -7.493 -25.5)
+    (stroke (width 0.12) (type solid)) (layer "F.SilkS") (tstamp d927535f-cc8d-43a7-b76f-f4dfc09666ee))
+  (fp_line (start -3.7 25.5) (end -10.5 25.5)
+    (stroke (width 0.12) (type solid)) (layer "F.SilkS") (tstamp 14f579d6-3318-4da8-b2d9-8e0f5db5a05f))
+  (fp_line (start -1.5 25.5) (end -1.1 25.5)
+    (stroke (width 0.12) (type solid)) (layer "F.SilkS") (tstamp 27ca2169-59ad-447f-a68f-0f29fc1977db))
+  (fp_line (start 1.1 25.5) (end 1.5 25.5)
+    (stroke (width 0.12) (type solid)) (layer "F.SilkS") (tstamp 16a8f7a9-c731-42b0-ad17-65e42091fbc1))
+  (fp_line (start 10.5 25.5) (end 3.7 25.5)
+    (stroke (width 0.12) (type solid)) (layer "F.SilkS") (tstamp b8906d14-e9f0-4ea1-a4b8-1449f821803d))
+  (fp_poly
+    (pts
+      (xy -1.5 -16.5)
+      (xy -3.5 -16.5)
+      (xy -3.5 -18.5)
+      (xy -1.5 -18.5)
+    )
+
+    (stroke (width 0.1) (type solid)) (fill solid) (layer "Dwgs.User") (tstamp 0eb1b416-28aa-4cdb-8690-d0725999584c))
+  (fp_poly
+    (pts
+      (xy -1.5 -14)
+      (xy -3.5 -14)
+      (xy -3.5 -16)
+      (xy -1.5 -16)
+    )
+
+    (stroke (width 0.1) (type solid)) (fill solid) (layer "Dwgs.User") (tstamp b7ce8cdf-b269-4c52-916a-d2629c4af864))
+  (fp_poly
+    (pts
+      (xy -1.5 -11.5)
+      (xy -3.5 -11.5)
+      (xy -3.5 -13.5)
+      (xy -1.5 -13.5)
+    )
+
+    (stroke (width 0.1) (type solid)) (fill solid) (layer "Dwgs.User") (tstamp bee0b376-7628-499e-9b17-86931ffd9a76))
+  (fp_poly
+    (pts
+      (xy 3.7 -20.2)
+      (xy -3.7 -20.2)
+      (xy -3.7 -24.9)
+      (xy 3.7 -24.9)
+    )
+
+    (stroke (width 0.1) (type solid)) (fill solid) (layer "Dwgs.User") (tstamp 7baa5a0a-0531-49db-a28e-4320d340b51d))
+  (fp_line (start -11 -26) (end 11 -26)
+    (stroke (width 0.12) (type solid)) (layer "F.CrtYd") (tstamp b1e4623a-da2c-4e95-985a-11008339ac1a))
+  (fp_line (start 11 26) (end -11 26)
+    (stroke (width 0.12) (type solid)) (layer "F.CrtYd") (tstamp a57e003b-e3d4-45cb-a054-c64b879581da))
+  (fp_line (start -10.5 -25.5) (end 10.5 -25.5)
+    (stroke (width 0.12) (type solid)) (layer "F.Fab") (tstamp 1b6101d5-274f-43cd-9025-c953950c0e0f))
+  (fp_line (start 10.5 25.5) (end -10.5 25.5)
+    (stroke (width 0.12) (type solid)) (layer "F.Fab") (tstamp ea1fb494-002a-4ad0-84df-ae0a640728e3))
+  (pad "1" smd rect (at -8.89 -24.13) (size 3.5 1.7) (drill (offset -0.9 0)) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 85cd1e1a-7322-488d-8ced-ff950da90267))
+  (pad "2" smd rect (at -8.89 -21.59) (size 3.5 1.7) (drill (offset -0.9 0)) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 139cc9b9-e743-4584-a232-3834f4ddca93))
+  (pad "3" smd rect (at -8.89 -19.05) (size 3.5 1.7) (drill (offset -0.9 0)) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 4c899508-a658-46fa-b2cb-0a2e6e1df5d4))
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