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0c1b9c3db3
'Software' was the directory everything that was not KiCad ended up in, which stopped describing anything a while ago - Validation and the web app are software too. Worse, it put the shared parts inside the firmware, where they read as the firmware's own. They are not. Effects/ has three consumers built from it: the firmware, Validation's bench, and the web app's controls, all generated from the same POT: comments by gen_effects.py. Audio/ has two - the bench compiles the same biquads, the same envelope followers and the same single_sample(), which is the whole reason a measurement on a workstation says anything about the pedal. Neither belongs under Firmware/, so neither is under it any more: Effects/ one file per effect Audio/ the DSP they are built from, and the audio loop Firmware/ the rest of what runs on the pedal, and the submodules WebMIDI/ the web app scripts/ what the build runs Validation/ unchanged Hardware/, Documentation/, Images/ CMakeLists.txt and the wrapper Makefile move to the top with them, because the build now consumes four of those directories and generates into a fifth. board.local and build/ come along; MIDI_CC_MAP.md is generated into Documentation/ rather than into the old Software/ root. scripts/ goes with the build rather than staying under the firmware, because six of the ten had nothing to do with the firmware: gen_effects.py reads Effects/ and writes to three different places, pow2/log2/quarter_sine generate Audio/'s tables, check-readme.py compares Effects/ against the README, and server.py serves the web app. Four of them are invoked from Validation, which was reaching into Firmware/ for tooling - the same burying this commit is undoing. The four that really are about the firmware are ELF checks the top-level build drives anyway, and a second scripts directory would only be a second place to look. C includes say "Audio/foo.h" and the generated map says "Effects/bar.h", with the repository root on the include path for both the firmware and the bench. Spelling the directory out rather than relying on a bare name is what keeps Audio/cycles.h shimmable: a quoted include searches the including file's own directory first. The submodules are renamed as well as moved. git mv updates their paths but leaves the section names, and 'Software/pico-sdk' surviving in .gitmodules would be the word this commit removes, still load-bearing. That meant the nested modules under pico-sdk too - six .git files pointing into .git/modules/Software - which is why 'git submodule update --init --recursive' is worth running once after pulling this. Verified rather than assumed: a clean configure and build, make check (failing only on the missing-eeprom case it already failed on), check-effects, all four analysis pages reproducing every series and drawing every chart, and a flash to the board that still measures a routed reverb where it did before. One latent bug fell out of it. bench/coeff declared only quarter_sine.h of the three generated math tables, and Audio/util.h includes pow2.h and log2.h as well - so building that target with an empty gen/ could never have worked. 'make bench' builds bench/bench first, which generates all three, so it stayed hidden until this rebuilt everything from nothing. Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
110 lines
2.8 KiB
Plaintext
110 lines
2.8 KiB
Plaintext
;
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; We want a target sample frequency of 48kHz, which
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; with 32-bit i2s data means a dot clock of 3.072MHz.
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;
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; We clock the rp2354 to 153.6MHz, which is exactly
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; 50x that dot clock frequency.
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;
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; We then use a PIO divider of 25, and make the PIO
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; program do 2 cycles per clock.
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;
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; i2s: FSYNC and each data bit is transmitted on the
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; falling edge of BCLK, so we set those bits the cycle
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; when BCLK goes low ("side 0") so that they are stable
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; on the rising edge ("side 1").
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;
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; The actual data is transmitted one cycle after FSYNC
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; goes low
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;
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.pio_version 1
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.program i2s_tx
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.fifo tx
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.clock_div 25
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.side_set 2
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.wrap_target
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out pins, 1 side 0b00 ; Cycle 0: FSYNC low. Output R0 (from previous frame)
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public start_tx:
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set x, 30 side 0b01
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loop_low:
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out pins, 1 side 0b00 ; Cycle 2: Output L31..L1
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jmp x-- loop_low side 0b01
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out pins, 1 side 0b10 ; Cycle 64: FSYNC high. Output L0
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set x, 30 side 0b11
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loop_high:
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out pins, 1 side 0b10 ; Cycle 66: Output R31..R1
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jmp x-- loop_high side 0b11
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.wrap
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% c-sdk {
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//
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// 'pin' is BCLK (MCU output)
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// 'pin+1' is FSYNC (MCU output)
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// 'pin+2' is DIN (MCU output! It's DIN from the CODEC standpoint!)
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// 'pin+3' is DOUT (MCU input! It's DOUT from the CODEC standpoint!)
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//
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static inline void i2s_tx_program_init(PIO pio, uint sm, uint offset, uint pin)
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{
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pio_sm_config c = i2s_tx_program_get_default_config(offset);
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pio_gpio_init(pio, pin);
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pio_gpio_init(pio, pin+1);
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pio_gpio_init(pio, pin+2);
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pio_gpio_init(pio, pin+3);
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// three output pins, one input
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pio_sm_set_pindirs_with_mask(pio, sm, 0b0111 << pin, 0b1111 << pin);
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// BCLK and FSYNC using sideset
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sm_config_set_sideset_pin_base(&c, pin);
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// DOUT using 'OUT' instruction
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sm_config_set_out_pins(&c, pin+2, 1);
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// Auto-pull, shift left (MSB first), 32 bits
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sm_config_set_out_shift(&c, false, true, 32);
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// Load and run the program
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pio_sm_init(pio, sm, offset + i2s_tx_offset_start_tx, &c);
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pio_sm_set_enabled(pio, sm, true);
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}
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%}
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.program i2s_rx
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.fifo rx
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.clock_div 25
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public start_rx:
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wait 1 jmppin ; wait for FSYNC going high
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wait 0 jmppin [1] ; wait for FSYNC going low, delay to sample middle
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.wrap_target
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set x, 30
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loop_left:
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in pins, 1
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jmp x-- loop_left
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in pins, 1 ; sample LSB of left channel
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set x, 30
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loop_right:
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in pins, 1
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jmp x-- loop_right
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in pins, 1 ; sample LSB of right channel
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.wrap
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% c-sdk {
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static inline void i2s_rx_program_init(PIO pio, uint sm, uint offset, uint pin)
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{
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pio_sm_config c = i2s_rx_program_get_default_config(offset);
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sm_config_set_jmp_pin(&c, pin+1); // FSYNC
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sm_config_set_in_pins(&c, pin+3); // DOUT
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// Auto-push, shift left (MSB first), 32 bits
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sm_config_set_in_shift(&c, false, true, 32);
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// Load and run the program
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pio_sm_init(pio, sm, offset + i2s_rx_offset_start_rx, &c);
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pio_sm_set_enabled(pio, sm, true);
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}
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%}
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