PexP

A White Rabbit timing receiver in PCIe (PCI Express) format.

Main Features

• FPGA
  • Altera Arria V GX (5AGXMA3D4F27I3N)
• CPLD
  • Xilinx Coolrunner-II (XC2C64A)
• Miscellaneous
  • On-board thermometer IC (DS18B20U+)
  • Unique 64-bit identifier (DS18B20U+)
• Front panel
  • 1x SFP port (White Rabbit compatible)
  • 5x LEMO/SMC programmable I/Os capable of driving 3.3V @ 50 ohm
  • 6x Programmable LEDs

Project Information

• Design files
• FPGA source code
• Hardware commissioning guide
• Description of the General Machine Timing System (GMT) @ GSI.
• Description of Timing Receivers for the GMT.

FPGA Gateware

git clone https://github.com/GSI-CS-CO/bel_projects.git

README.md => See "Build Gateware(s)"

Commissioning

Instructions for testing and commissioning can be found here:

https://wiki.gsi.de/TOS/Timing/TimingSystemPEXPTestingAndCommissioning

Photos

Contacts

Commercial Producers

• Cosylab, Slovenia

General Question About the Project

• Alexander Hahn, GSI, Germany

Status

Date	Event
21-10-2019	Created project and repository on OHWR
01-01-2020	Received first prototypes (REVA)
01-08-2020	Received first revision (REVB)
01-09-2023	Received first of series (REVB)