mirror of
https://github.com/fairwaves/umtrx-schematics.git
synced 2025-04-03 04:27:02 +00:00
Checking in UmTRXv2.1 schematics.
This commit is contained in:
parent
e0be8240c5
commit
1300c736bc
@ -16,6 +16,11 @@ Structure
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- bom - Bill of Materials exported from the Altium Designer
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- pdf - schematics and assembly drawings exported from the Altium Designer
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- pictures - 3D model pictures and photos
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- umtrx-v2.1 - files related to UmTRXv2.1 boards
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- altium - design files in Altium Designer format
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- bom - Bill of Materials exported from the Altium Designer
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- pdf - schematics and assembly drawings exported from the Altium Designer
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- pictures - 3D model pictures and photos
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- umsel-v1 - files related to UmSELv1 preselector mezzanine boards (GSM900 and GSM1800 versions)
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- altium - design files in Altium Designer format
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- bom - Bill of Materials exported from the Altium Designer
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14
umtrx-v2.1/What new in UmTRXv2.1.txt
Normal file
14
umtrx-v2.1/What new in UmTRXv2.1.txt
Normal file
@ -0,0 +1,14 @@
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Whats new in UmTRXv2.1
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1. C167 Removed and DC supply connector PJ-002AH-SMT now placed there for lab users.
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2. Fixed unrouted GND track under the fpga, which wasn't issue because of redundant.
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3. Both FAN1 and FAN2 now can be supplied from +6V or +8..28V through R172/R172' or R171/R171'.
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4. PVDDSPI33 of LMS's connected to +2.5VLMS (L13) because of SPI port is 2.5VCMOS at FPGA side.
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5. OHM4 component footprint fixed to place it from top side (issue 32).
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6. LMS output matching capasitor C96'= 3pF added (issue 41).
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7. DC/DC syncro problem fixed. C23 = 100pF added to sync circuit of DC/DC converters (issue 42).
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8. Thermosensors added for both LMS. Both connected to EEPROM I2C bus.
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9. For better performance, +3.3VLMS supplied from DC/DC+3.3V via inductor filter instead of noisy U29.
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10. Fixed netlabels of pins AA1 and AB4 of FPGA and S1 signed "RESET", but S2 signed "SAFE" (issue 40).
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11. Returned MCX connectors for all RF signals, but U.FL connectors still can be used at the same places.
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12. GPS, CLK and PPS now with onboard through hole SMA connectors at the edge of board.
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umtrx-v2.1/altium/Clocking.SchDoc
Normal file
LOADING design file
umtrx-v2.1/altium/EEpromConfig.SchDoc
Normal file
LOADING design file
umtrx-v2.1/altium/FPGA_RAM.SchDoc
Normal file
LOADING design file
umtrx-v2.1/altium/GBEthernet.SchDoc
Normal file
LOADING design file
umtrx-v2.1/altium/LMS.SchDoc
Normal file
LOADING design file
umtrx-v2.1/altium/PwrAndBias.SchDoc
Normal file
LOADING design file
umtrx-v2.1/altium/Total.SchDoc
Normal file
LOADING design file
276
umtrx-v2.1/altium/UmTRXv21.OutJob
Normal file
276
umtrx-v2.1/altium/UmTRXv21.OutJob
Normal file
@ -0,0 +1,276 @@
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||||
RelativeOutputPath4=C:\Users\Public\Documents\Altium\AD 10\Projects\UmTRXv21\Project\Project Outputs\
|
||||
OpenOutputs4=1
|
||||
AddToProject4=1
|
||||
TimestampFolder4=0
|
||||
UseOutputName4=0
|
||||
OpenODBOutput4=0
|
||||
OpenGerberOutput4=1
|
||||
OpenNCDrillOutput4=1
|
||||
OpenIPCOutput4=0
|
||||
EnableReload4=1
|
||||
RelativeOutputPath5=C:\Users\Public\Documents\Altium\AD 10\Projects\UmTRXv21\Project\Project Outputs\
|
||||
OpenOutputs5=0
|
||||
RelativeOutputPath6=C:\Users\Public\Documents\Altium\AD 10\Projects\UmTRXv21\Project\Project Outputs\
|
||||
OpenOutputs6=0
|
||||
AddToProject6=0
|
||||
TimestampFolder6=0
|
||||
UseOutputName6=0
|
||||
OpenODBOutput6=0
|
||||
OpenGerberOutput6=0
|
||||
OpenNCDrillOutput6=0
|
||||
OpenIPCOutput6=0
|
||||
EnableReload6=0
|
||||
RelativeOutputPath7=C:\Users\Public\Documents\Altium\AD 10\Projects\UmTRXv21\Project\Project Outputs\
|
||||
OpenOutputs7=0
|
||||
AddToProject7=0
|
||||
TimestampFolder7=0
|
||||
UseOutputName7=0
|
||||
OpenODBOutput7=0
|
||||
OpenGerberOutput7=0
|
||||
OpenNCDrillOutput7=0
|
||||
OpenIPCOutput7=0
|
||||
EnableReload7=0
|
||||
|
2710
umtrx-v2.1/altium/UmTRXv21.PRJPCB
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2710
umtrx-v2.1/altium/UmTRXv21.PRJPCB
Normal file
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Load Diff
BIN
umtrx-v2.1/bom/UmTRXv21_20dBm_TCXO_BOM_021212.xls
Normal file
BIN
umtrx-v2.1/bom/UmTRXv21_20dBm_TCXO_BOM_021212.xls
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BIN
umtrx-v2.1/pdf/UmTRXv2.1_20dBm_TCXO_SCH.pdf
Normal file
BIN
umtrx-v2.1/pdf/UmTRXv2.1_20dBm_TCXO_SCH.pdf
Normal file
BIN
umtrx-v2.1/pdf/UmTRXv2.1_FULL_Assembly.pdf
Normal file
BIN
umtrx-v2.1/pdf/UmTRXv2.1_FULL_Assembly.pdf
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BIN
umtrx-v2.1/pdf/UmTRXv2.1_FULL_SCH.pdf
Normal file
BIN
umtrx-v2.1/pdf/UmTRXv2.1_FULL_SCH.pdf
Normal file
BIN
umtrx-v2.1/pictures/UmTRXv21_20dBm_TCXO.png
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umtrx-v2.1/pictures/UmTRXv21_20dBm_TCXO.png
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umtrx-v2.1/pictures/UmTRXv21_all_comp.png
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umtrx-v2.1/pictures/UmTRXv21_all_comp.png
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umtrx-v2.1/pictures/UmTRXv21_empty.png
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umtrx-v2.1/pictures/UmTRXv21_empty.png
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After ![]() (image error) Size: 279 KiB |
Loading…
Reference in New Issue
Block a user