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mirror of https://github.com/uob-hep-cad/uob-hep-pc072.git synced 2025-03-14 17:34:55 +00:00
Commit Graph

8 Commits

Author SHA1 Message Date
David Cussans
8c99702206 Pushing files flagged as changed by GIT 2025-02-10 15:19:29 +00:00
Peter Hastings
79075ed892 854S01AKILF Hidden symbol pins!
Hi, not too sure you will be happy with my workaround for this but whoever made the schematic symbol has hidden the power and gnd pins. GND is fine but the "VDD" rail will not short to the 3V3 provided. I have altered settings within Concept HDL to let me use a synonym (which does work but not on the logical net set by the symbol) to short the 3.3V and VDD but it doesn't work. I have used a ferrite bead to join the voltages together and some bypass caps.
2024-06-26 11:17:31 +01:00
Peter Hastings
4fb5774435 timing sheet archived in oxflib component folder
Just in case the next steps screw it up completely
2024-06-21 14:31:16 +01:00
Peter Hastings
d4c4a48a88 Mux task remains 2024-06-21 11:39:15 +01:00
Peter Hastings
734141d6f9 Two items left to implement 2024-06-21 10:23:04 +01:00
Peter Hastings
3366bbc6d1 another snapshot 2024-06-19 11:18:54 +01:00
Peter Hastings
36e0a1d1fb second item completed 2024-06-19 10:05:30 +01:00
Peter Hastings
5fee1e53f3 first item added
the 2x1 header for shorting reset to gnd
2024-06-19 09:44:37 +01:00