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David Cussans 825b121be1 Copied definitive BoM into project. Added some images used for electrical safety review
2025-01-24 17:38:56 +00:00
hardware Copied definitive BoM into project. Added some images used for electrical safety review 2025-01-24 17:38:56 +00:00
images Copied definitive BoM into project. Added some images used for electrical safety review 2025-01-24 17:38:56 +00:00
.gitignore Edited tongue2 schematic to include just the tongue-2 uTCA AMC connector ( not both tongue1 and tongue2 ) 2023-02-02 15:12:11 +00:00
LICENSE Removing dummy file. Adding module_order.dat - generated automatically by Cadence. 2023-01-16 10:39:59 +00:00
README.md Update README.md 2025-01-23 10:42:16 +00:00

README.md

uob-hep-pc072

DUNE Timing System MicroTCA Interface Board(MIB).

Schematic capture in Cadence DE-HDL. PCB Layout in Cadence Allegro.

Design files for the current (v3) board at https://github.com/uob-hep-cad/uob-hep-pc072/tree/main/hardware/Cadence/top/mtca_interface_board_reocc/top_mib_v3 (project file https://github.com/uob-hep-cad/uob-hep-pc072/blob/main/hardware/Cadence/top/top_mib_v3.cpm)

Design files for the tongue-2 board at https://github.com/uob-hep-cad/uob-hep-pc072/tree/main/hardware/Cadence/top/mtca_interface_board_reocc/mib_tongue2 (project file https://github.com/uob-hep-cad/uob-hep-pc072/blob/main/hardware/Cadence/top/top_mib_v3.cpm)

Schematic capture and PCB layout of the original (v1) version done at University of Pensylvania by Godwin Meyers in Cadence Orcad/Allegro

The v1 design translated to Cadence Allegro Design Entry HDL by Elgris Technologies

Changes to v1 design done by Magnus Loutit and David Cussans to produce the v2 and then v3 design

PCB layout of the v3 design done at the University of Oxford by Pete Hastings

The MIB v2 onwards has no ADN2814 CDR - recovery of clock done directly by Si5395 PLL

List of changes w.r.t. v0.1 MIB at https://webapps-pp.bris.ac.uk/elog/DUNE/34