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README.md |
README.md
uob-hep-pc072
DUNE Timing System MicroTCA Interface Board(MIB).
Bug-fixed version of board with schematic capture done at University of Pensylvania by Godwin Meyers in Cadence Orcad
Translated to Cadence Allegro Design Entry HDL by Elgris Technologies
Changes to original design done by Magnus Loutit and David Cussans
This design has no ADN2814 CDR - recovery of clock done directly by Si5395 PLL
List of changes w.r.t. v0.1 MIB at https://webapps-pp.bris.ac.uk/elog/DUNE/34