73 lines
7.1 KiB
Plaintext
73 lines
7.1 KiB
Plaintext
Protel Design System Design Rule Check
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PCB File : C:\Users\Taiping\Documents\MidnightSun\hardware\MSXII-PreCharge\PCB1.PcbDoc
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Date : 12/4/2016
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Time : 7:02:26 PM
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Processing Rule : Room Sheet1 (Bounding Region = (0mil, 0mil, 2000mil, 1000mil) (Disabled)(All)
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Rule Violations :0
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Processing Rule : Power Plane Connect Rule(Relief Connect )(Expansion=20mil) (Conductor Width=10mil) (Air Gap=10mil) (Entries=4) (All)
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Rule Violations :0
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Processing Rule : Clearance Constraint (Gap=7.874mil) (All),(All)
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Rule Violations :0
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Processing Rule : Width Constraint (Min=7.874mil) (Max=30mil) (Preferred=7.874mil) (All)
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Rule Violations :0
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Processing Rule : Modified Polygon (Allow modified: No), (Allow shelved: No)
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Rule Violations :0
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Processing Rule : Net Antennae (Tolerance=0mil) (All)
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Rule Violations :0
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Processing Rule : Silk to Silk (Clearance=10mil) (All),(All)
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Violation between Silk To Silk Clearance Constraint: (9.273mil < 10mil) Between Text "P3" (2066.929mil,4311.024mil) on Top Overlay And Track (2047.244mil,3988.189mil)(2047.244mil,4921.26mil) on Top Overlay Silk Text to Silk Clearance [9.273mil]
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Rule Violations :1
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Processing Rule : Silk To Solder Mask (Clearance=10mil) (IsPad),(All)
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Violation between Silk To Solder Mask Clearance Constraint: (4.432mil < 10mil) Between Track (3708.898mil,3248.425mil)(3708.898mil,3258.425mil) on Top Overlay And Pad P1-2(3667.323mil,3283.465mil) on Top Layer [Top Overlay] to [Top Solder] clearance [4.432mil]
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Violation between Silk To Solder Mask Clearance Constraint: (4.354mil < 10mil) Between Track (3708.898mil,3308.425mil)(3708.898mil,3323.425mil) on Top Overlay And Pad P1-2(3667.323mil,3283.465mil) on Top Layer [Top Overlay] to [Top Solder] clearance [4.354mil]
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Violation between Silk To Solder Mask Clearance Constraint: (3.268mil < 10mil) Between Track (3708.898mil,3248.425mil)(3708.898mil,3258.425mil) on Top Overlay And Pad P1-1(3667.323mil,3224.41mil) on Top Layer [Top Overlay] to [Top Solder] clearance [3.268mil]
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Violation between Silk To Solder Mask Clearance Constraint: (5.236mil < 10mil) Between Track (3708.898mil,3183.425mil)(3708.898mil,3198.425mil) on Top Overlay And Pad P1-1(3667.323mil,3224.41mil) on Top Layer [Top Overlay] to [Top Solder] clearance [5.236mil]
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Violation between Silk To Solder Mask Clearance Constraint: (5.04mil < 10mil) Between Track (3708.898mil,3408.425mil)(3743.898mil,3408.425mil) on Top Overlay And Pad P1-(3818.898mil,3385.827mil) on Top Layer [Top Overlay] to [Top Solder] clearance [5.04mil]
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Violation between Silk To Solder Mask Clearance Constraint: (5.04mil < 10mil) Between Track (3893.898mil,3098.425mil)(3893.898mil,3408.425mil) on Top Overlay And Pad P1-(3818.898mil,3385.827mil) on Top Layer [Top Overlay] to [Top Solder] clearance [5.04mil]
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Violation between Silk To Solder Mask Clearance Constraint: (5.04mil < 10mil) Between Track (3688.898mil,3098.425mil)(3743.898mil,3098.425mil) on Top Overlay And Pad P1-(3818.898mil,3122.047mil) on Top Layer [Top Overlay] to [Top Solder] clearance [5.04mil]
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Violation between Silk To Solder Mask Clearance Constraint: (5.04mil < 10mil) Between Track (3893.898mil,3098.425mil)(3893.898mil,3408.425mil) on Top Overlay And Pad P1-(3818.898mil,3122.047mil) on Top Layer [Top Overlay] to [Top Solder] clearance [5.04mil]
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Violation between Silk To Solder Mask Clearance Constraint: (5.315mil < 10mil) Between Track (2080.354mil,3080.236mil)(2295.354mil,3080.236mil) on Top Overlay And Pad P2-(2165.354mil,3110.236mil) on Top Layer [Top Overlay] to [Top Solder] clearance [5.315mil]
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Violation between Silk To Solder Mask Clearance Constraint: (5.12mil < 10mil) Between Track (2295.354mil,3205.236mil)(2295.354mil,3210.236mil) on Top Overlay And Pad P2-2(2297.244mil,3232.283mil) on Top Layer [Top Overlay] to [Top Solder] clearance [5.12mil]
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Violation between Silk To Solder Mask Clearance Constraint: (6.026mil < 10mil) Between Track (2295.354mil,3255.236mil)(2295.354mil,3330.236mil) on Top Overlay And Pad P2-2(2297.244mil,3232.283mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.026mil]
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Violation between Silk To Solder Mask Clearance Constraint: (5.354mil < 10mil) Between Track (2295.354mil,3205.236mil)(2295.354mil,3210.236mil) on Top Overlay And Pad P2-1(2297.244mil,3183.071mil) on Top Layer [Top Overlay] to [Top Solder] clearance [5.354mil]
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Violation between Silk To Solder Mask Clearance Constraint: (6.024mil < 10mil) Between Track (2295.354mil,3080.236mil)(2295.354mil,3160.236mil) on Top Overlay And Pad P2-1(2297.244mil,3183.071mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.024mil]
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Violation between Silk To Solder Mask Clearance Constraint: (4.37mil < 10mil) Between Track (2080.354mil,3330.236mil)(2295.354mil,3330.236mil) on Top Overlay And Pad P2-(2165.354mil,3301.181mil) on Top Layer [Top Overlay] to [Top Solder] clearance [4.37mil]
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Violation between Silk To Solder Mask Clearance Constraint: (4.751mil < 10mil) Between Track (3622.047mil,3877.953mil)(3622.047mil,4921.26mil) on Top Overlay And Pad U1-2(3661.417mil,4724.409mil) on Multi-Layer [Top Overlay] to [Top Solder] clearance [4.751mil]
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Rule Violations :15
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Processing Rule : Minimum Solder Mask Sliver (Gap=10mil) (All),(All)
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Violation between Minimum Solder Mask Sliver Constraint: (9.717mil < 10mil) Between Pad C1-1(3070.866mil,3236.22mil) on Top Layer And Pad C1-2(3070.866mil,3289.37mil) on Top Layer [Top Solder] Mask Sliver [9.717mil]
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Violation between Minimum Solder Mask Sliver Constraint: (9.717mil < 10mil) Between Pad DS1-1(2244.095mil,3385.827mil) on Top Layer And Pad R4-2(2248.032mil,3437.008mil) on Top Layer [Top Solder] Mask Sliver [9.717mil]
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Violation between Minimum Solder Mask Sliver Constraint: (9.717mil < 10mil) Between Pad DS1-2(2303.15mil,3385.827mil) on Top Layer And Pad R4-1(2299.213mil,3437.008mil) on Top Layer [Top Solder] Mask Sliver [9.717mil]
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Violation between Minimum Solder Mask Sliver Constraint: (5.78mil < 10mil) Between Pad Q1-2(2637.795mil,3386.221mil) on Top Layer And Pad Q1-1(2600.394mil,3386.221mil) on Top Layer [Top Solder] Mask Sliver [5.78mil]
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Violation between Minimum Solder Mask Sliver Constraint: (5.779mil < 10mil) Between Pad Q1-3(2675.197mil,3386.221mil) on Top Layer And Pad Q1-2(2637.795mil,3386.221mil) on Top Layer [Top Solder] Mask Sliver [5.779mil]
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Violation between Minimum Solder Mask Sliver Constraint: (5.779mil < 10mil) Between Pad Q1-5(2637.795mil,3493.701mil) on Top Layer And Pad Q1-4(2675.197mil,3493.701mil) on Top Layer [Top Solder] Mask Sliver [5.779mil]
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Violation between Minimum Solder Mask Sliver Constraint: (5.78mil < 10mil) Between Pad Q1-6(2600.394mil,3493.701mil) on Top Layer And Pad Q1-5(2637.795mil,3493.701mil) on Top Layer [Top Solder] Mask Sliver [5.78mil]
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Rule Violations :7
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Processing Rule : Hole To Hole Clearance (Gap=10mil) (All),(All)
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Rule Violations :0
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Processing Rule : Hole Size Constraint (Min=1mil) (Max=100mil) (All)
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Rule Violations :0
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Processing Rule : Height Constraint (Min=0mil) (Max=1000mil) (Prefered=500mil) (All)
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Rule Violations :0
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Processing Rule : Un-Routed Net Constraint ( (All) )
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Rule Violations :0
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Processing Rule : Short-Circuit Constraint (Allowed=No) (All),(All)
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Rule Violations :0
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Violations Detected : 23
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Time Elapsed : 00:00:00 |