MUREX/electrical
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Feat: Updated board constraints, fixed various violations

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xamuil2 2023-07-06 12:52:39 +08:00
parent 00f7a2b218
commit 8f53d2ec4a
2 changed files with 7987 additions and 8902 deletions

power/power.kicad_pcb
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LOADING design file

10
power/power.kicad_pro
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@ -113,17 +113,17 @@
"max_error": 0.005,
"min_clearance": 0.0,
"min_connection": 0.0,
"min_copper_edge_clearance": 0.0,
"min_copper_edge_clearance": 0.3,
"min_hole_clearance": 0.25,
"min_hole_to_hole": 0.25,
"min_microvia_diameter": 0.19999999999999998,
"min_microvia_drill": 0.09999999999999999,
"min_resolved_spokes": 2,
"min_silk_clearance": 0.0,
"min_text_height": 0.7999999999999999,
"min_text_thickness": 0.08,
"min_silk_clearance": 0.15,
"min_text_height": 1.0,
"min_text_thickness": 0.15,
"min_through_hole_diameter": 0.3,
"min_track_width": 0.0,
"min_track_width": 0.09,
"min_via_annular_width": 0.09999999999999999,
"min_via_diameter": 0.5,
"solder_mask_clearance": 0.0,