MUREX/electrical
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electrical/esc/anyesc/jlcpcb/gerber
History
Max Liu f0ec3aa968 Feat[2025_SID, float2025_SID]: Add 2025 SIDs
2025-05-14 15:00:14 -04:00
..
anyesc-CuBottom.gbr
Feat[2025_SID, float2025_SID]: Add 2025 SIDs
2025-05-14 15:00:14 -04:00
anyesc-CuIn1.gbr
Feat[2025_SID, float2025_SID]: Add 2025 SIDs
2025-05-14 15:00:14 -04:00
anyesc-CuIn2.gbr
Feat[2025_SID, float2025_SID]: Add 2025 SIDs
2025-05-14 15:00:14 -04:00
anyesc-CuTop.gbr
Feat[2025_SID, float2025_SID]: Add 2025 SIDs
2025-05-14 15:00:14 -04:00
anyesc-EdgeCuts.gbr
Feat[2025_SID, float2025_SID]: Add 2025 SIDs
2025-05-14 15:00:14 -04:00
anyesc-MaskBottom.gbr
Feat[2025_SID, float2025_SID]: Add 2025 SIDs
2025-05-14 15:00:14 -04:00
anyesc-MaskTop.gbr
Feat[2025_SID, float2025_SID]: Add 2025 SIDs
2025-05-14 15:00:14 -04:00
anyesc-NPTH-drl_map.pdf
Feat[2025_SID, float2025_SID]: Add 2025 SIDs
2025-05-14 15:00:14 -04:00
anyesc-NPTH.drl
Feat[2025_SID, float2025_SID]: Add 2025 SIDs
2025-05-14 15:00:14 -04:00
anyesc-PasteBottom.gbr
Feat[2025_SID, float2025_SID]: Add 2025 SIDs
2025-05-14 15:00:14 -04:00
anyesc-PasteTop.gbr
Feat[2025_SID, float2025_SID]: Add 2025 SIDs
2025-05-14 15:00:14 -04:00
anyesc-PTH-drl_map.pdf
Feat[2025_SID, float2025_SID]: Add 2025 SIDs
2025-05-14 15:00:14 -04:00
anyesc-PTH.drl
Feat[2025_SID, float2025_SID]: Add 2025 SIDs
2025-05-14 15:00:14 -04:00
anyesc-SilkBottom.gbr
Feat[2025_SID, float2025_SID]: Add 2025 SIDs
2025-05-14 15:00:14 -04:00
anyesc-SilkTop.gbr
Feat[2025_SID, float2025_SID]: Add 2025 SIDs
2025-05-14 15:00:14 -04:00
anyesc-VScore.gbr
Feat[2025_SID, float2025_SID]: Add 2025 SIDs
2025-05-14 15:00:14 -04:00