McRaeAlex/USB2SPDIF
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Signed-off-by: jyzhiyu <zhiyu.zheng@itead.cc>

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This commit is contained in:
jyzhiyu 2016-01-22 17:33:08 +08:00
parent 85aaa90ae5
commit 1483e353d8
141 changed files with 22975 additions and 19 deletions

12
board/hdl/PadUsageReport.out Normal file
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A!PAD_NAME!REC_NUMBER!LAYER!FIXFLAG!VIAFLAG!PADSHAPE1!PADWIDTH!PADHGHT!PADXOFF!PADYOFF!PADFLASH!PADSHAPENAME!TRELSHAPE1!TRELWIDTH!TRELHGHT!TRELXOFF!TRELYOFF!TRELFLASH!TRELSHAPENAME!APADSHAPE1!APADWIDTH!APADHGHT!APADXOFF!APADYOFF!APADFLASH!APADSHAPENAME!
J!Z:/PCBSymbol/lqfp100-P0_5.dra!Fri Jan 22 17:06:29 2016!-9.500!-9.500!13.360!13.360!0.001!millimeters!!10.400000 mil!2!UP TO DATE!
S!OX1_65Y0_27T!00001!TOP!o!v!OBLONG_X!1.650!0.270!0.000!0.000!!!!0.000!0.000!0.000!0.000!!!!0.000!0.000!0.000!0.000!!!
S!OX1_65Y0_27T!00002!internal_pad_def!o!v!!0.000!0.000!0.000!0.000!!!!0.000!0.000!0.000!0.000!!!!0.000!0.000!0.000!0.000!!!
S!OX1_65Y0_27T!00003!BOTTOM!o!v!!0.000!0.000!0.000!0.000!!!!0.000!0.000!0.000!0.000!!!!0.000!0.000!0.000!0.000!!!
S!OX1_65Y0_27T!00004!~TSM!o!v!OBLONG_X!1.850!0.470!0.000!0.000!!!!!!!!!!!!!!!!!
S!OX1_65Y0_27T!00005!~BSM!o!v!!0.000!0.000!0.000!0.000!!!!!!!!!!!!!!!!!
S!OX1_65Y0_27T!00006!~TPM!o!v!OBLONG_X!1.650!0.270!0.000!0.000!!!!!!!!!!!!!!!!!
S!OX1_65Y0_27T!00007!~BPM!o!v!!0.000!0.000!0.000!0.000!!!!!!!!!!!!!!!!!
S!OX1_65Y0_27T!00008!~TFM!o!v!!0.000!0.000!0.000!0.000!!!!!!!!!!!!!!!!!
S!OX1_65Y0_27T!00009!~BFM!o!v!!0.000!0.000!0.000!0.000!!!!!!!!!!!!!!!!!
S!OX1_65Y0_27T!00010!~DRILL!o!v!0.000!0.000!0.000!0.000!0.000!!P!!n!!!!!!CIRCLE_DRILL!CIRCLE_DRILL!0.000!0.000!!!!

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board/hdl/adw/shoppingCart.xml Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<sc:shoppingCart xmlns:sc="http://www.cadence.com/SPB/shopping_cart" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" checksum="0">
<component cell="atsam3u1cb-au" library="usb2iterface_lib" partname="ATSAM3U1CB-AU" partno="" quantity="1" >
<property name="PACK_TYPE" value="SMT"/>
</component>
<component cell="usb_microf" library="connector" partname="USB_MICROF" partno="00.29.08.0006" quantity="1" >
<property name="INDEX" value="1"/>
<property name="VALUE" value="microUSB_B_4dip"/>
</component>
<component cell="res" library="discrete" partname="RES" partno="00.22.01.0039" quantity="1" >
<property name="INDEX" value="1"/>
<property name="VALUE" value="39R|J|0603"/>
</component>
<component cell="tvs" library="diode" partname="TVS" partno="06.00.01.0046" quantity="1" >
<property name="INDEX" value="1"/>
<property name="VALUE" value="SMBJ20A"/>
</component>
</sc:shoppingCart>

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board/hdl/cds.lib Normal file
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DEFINE usb2iterface_lib worklib
INCLUDE $CONCEPT_INST_DIR/share/cdssetup/cds.lib

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board/hdl/log/extract.log Normal file
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PAD_DEF

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board/hdl/signoise.run/cases.cfg,1 Normal file
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(SisCases
(cases
(case1 "Default Settings" ) ) )

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board/hdl/temp/ConCM.log Normal file
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ConceptHDL - Constraint Manager Synchronization Log
====================================================
----------------------------
Running audit on all the signal models present in design.
----------------------------
----------------------------
Audit revealed 0 instances in the design with missing model information.
----------------------------

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board/hdl/temp/backannotate.log Normal file
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Processing drawing @usb2iterface_lib.sch(sch_1):page1

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board/hdl/temp/cfg_package.log Normal file
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board/hdl/temp/cfg_pic.log Normal file
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board/hdl/temp/cfg_sch.bat Normal file
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van.exe -q -nolinks -sironly -cdslib cds.lib -module usb2iterface_lib.glbl:sch_cfg_package -lib usb2iterface_lib -view sch_cfg_package -globals usb2iterface_lib.glbl:sch_cfg_package
sch;usb2iterface_lib;sch_1;C:\Users\jyzhiyu\Dropbox\work\USB2SPDIF\board\hdl\worklib\sch\sch_1\verilog.v;2;1

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board/hdl/temp/cfg_verilog.log Normal file
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board/hdl/temp/cfg_vhdl.log Normal file
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board/hdl/temp/csdirect.log Normal file
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CSDirect 16.5-S056 (v16-5-13EB)
Netlisting block sch
Processing page 1
WARNING(SPCOCD-22): The specified property: SPLIT_INST = TRUE was ignored for the instance: atsam3u1cb-au, PATH: i3 because two split properties are specified for the instance. Ensure that you specify either SPLIT_INST_NAME or SPLIT_INST for one instance.
Object description:
Page: 1 Instance: i3 Cell name: atsam3u1cb-au
WARNING(SPCOCD-22): The specified property: SPLIT_INST = TRUE was ignored for the instance: atsam3u1cb-au, PATH: i2 because two split properties are specified for the instance. Ensure that you specify either SPLIT_INST_NAME or SPLIT_INST for one instance.
Object description:
Page: 1 Instance: i2 Cell name: atsam3u1cb-au
WARNING(SPCOCD-22): The specified property: SPLIT_INST = TRUE was ignored for the instance: atsam3u1cb-au, PATH: i1 because two split properties are specified for the instance. Ensure that you specify either SPLIT_INST_NAME or SPLIT_INST for one instance.
Object description:
Page: 1 Instance: i1 Cell name: atsam3u1cb-au

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board/hdl/temp/hdldir.log Normal file
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HDL Direct 16.5-S048 (v16-5-13DK) 9/23/2013
Copyright (C) 1996 Cadence Design Systems, Inc.
Processing cell view: SCH(SCH_1)
Generating for languages: Verilog
Processing page 1
WARNING(SPCOHD-22): The specified property: ATSAM3U1CB-AU = I3 was ignored for the instance: SPLIT_INST, PATH: true because two split properties are specified for the instance. Ensure that you specify either SPLIT_INST_NAME or SPLIT_INST for one instance.
Object description:
Page: 1 Instance: I3 Cell name: ATSAM3U1CB-AU
WARNING(SPCOHD-22): The specified property: ATSAM3U1CB-AU = I2 was ignored for the instance: SPLIT_INST, PATH: true because two split properties are specified for the instance. Ensure that you specify either SPLIT_INST_NAME or SPLIT_INST for one instance.
Object description:
Page: 1 Instance: I2 Cell name: ATSAM3U1CB-AU
WARNING(SPCOHD-22): The specified property: ATSAM3U1CB-AU = I1 was ignored for the instance: SPLIT_INST, PATH: true because two split properties are specified for the instance. Ensure that you specify either SPLIT_INST_NAME or SPLIT_INST for one instance.
Object description:
Page: 1 Instance: I1 Cell name: ATSAM3U1CB-AU
Total number of pages: 1
Generating Output File lib.cell:view usb2iterface_lib.sch:sch_1
Design Entry HDL Direct: Created Netlist.

0
board/hdl/temp/mkdefcfg.log Normal file
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board/hdl/temp/netassembler.dat Normal file
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sch usb2iterface_lib cfg_package
1ns/1ns

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board/hdl/temp/netassembler.log Normal file
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Reading Configuration: usb2iterface_lib sch cfg_package
Calling HDLDirect with lib.cell:view usb2iterface_lib.sch:sch_1
*********************************************************************
Netlisting Errors : 0
Netlisting Warnings : 3
*********************************************************************
HDL Direct 16.5-S048 (v16-5-13DK) 9/23/2013
Copyright (C) 1996 Cadence Design Systems, Inc.
Processing cell view: SCH(SCH_1)
Generating for languages: Verilog
Processing page 1
WARNING(SPCOHD-22): The specified property: ATSAM3U1CB-AU = I3 was ignored for the instance: SPLIT_INST, PATH: true because two split properties are specified for the instance. Ensure that you specify either SPLIT_INST_NAME or SPLIT_INST for one instance.
Object description:
Page: 1 Instance: I3 Cell name: ATSAM3U1CB-AU
WARNING(SPCOHD-22): The specified property: ATSAM3U1CB-AU = I2 was ignored for the instance: SPLIT_INST, PATH: true because two split properties are specified for the instance. Ensure that you specify either SPLIT_INST_NAME or SPLIT_INST for one instance.
Object description:
Page: 1 Instance: I2 Cell name: ATSAM3U1CB-AU
WARNING(SPCOHD-22): The specified property: ATSAM3U1CB-AU = I1 was ignored for the instance: SPLIT_INST, PATH: true because two split properties are specified for the instance. Ensure that you specify either SPLIT_INST_NAME or SPLIT_INST for one instance.
Object description:
Page: 1 Instance: I1 Cell name: ATSAM3U1CB-AU
Total number of pages: 1
Generating Output File lib.cell:view usb2iterface_lib.sch:sch_1
Design Entry HDL Direct: Created Netlist.
*********************************************************************
Total Netlisting Errors : 0
Total Netlisting Warnings : 3
Error (Marker) File : temp/pkgNetlist.mkr
*********************************************************************
van.exe -q -nolinks -sironly -cdslib cds.lib -module "usb2iterface_lib.glbl:sch_cfg_package" -lib "usb2iterface_lib" -view "sch_cfg_package" -define VAN -globals "usb2iterface_lib.glbl:sch_cfg_package"
van.exe -nolinks -sironly -cdslib cds.lib "C:\Users\jyzhiyu\Dropbox\work\USB2SPDIF\board\hdl\worklib\sch\sch_1\verilog.v" -lib "usb2iterface_lib" -view sch_1 -instanceview sch_1 -instanceview entity -define VAN -globals "usb2iterface_lib.glbl:sch_cfg_package"

4
board/hdl/temp/packagerxl.bat Normal file
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echo off
netassembler
concept2cm -forward -export -proj "C:\Users\jyzhiyu\Dropbox\work\USB2SPDIF\board\hdl\usb2iterface.cpm"
pxl.exe -proj "C:\Users\jyzhiyu\Dropbox\work\USB2SPDIF\board\hdl\usb2iterface.cpm" -nonetassembler

77
board/hdl/temp/pkgNetlist.mkr Normal file
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(marker_file
(version 1.0)
(markers
(
(tool "HDL_Direct")
(class "SCHEMATIC")
(severity 30)
(error_num 1)
(short_msg "WARNING(SPCOHD-22): The specified property: ATSAM3U1CB-AU = I3 was ignored for the instance: SPLIT_INST, PATH: true because two split properties are specified for the instance. Ensure that you specify either SPLIT_INST_NAME or SPLIT_INST for one instance.")
(long_msg "Severity : Warning (HDL Direct)
Description : WARNING(SPCOHD-22): The specified property: ATSAM3U1CB-AU = I3 was ignored for the instance: SPLIT_INST, PATH: true because two split properties are specified for the instance. Ensure that you specify either SPLIT_INST_NAME or SPLIT_INST for one instance.
Object dump:
{
page: 1
instance: I3
cell name: ATSAM3U1CB-AU
}
")
(location
(
(object_kind "Instance")
(canonical_name "_!drawerror inst I3;")
(parent_canonical_name "DRAWERROR INST I3")
(drawing_name "@usb2iterface_lib.sch(sch_1):page1")
)
)
)
(
(tool "HDL_Direct")
(class "SCHEMATIC")
(severity 30)
(error_num 2)
(short_msg "WARNING(SPCOHD-22): The specified property: ATSAM3U1CB-AU = I2 was ignored for the instance: SPLIT_INST, PATH: true because two split properties are specified for the instance. Ensure that you specify either SPLIT_INST_NAME or SPLIT_INST for one instance.")
(long_msg "Severity : Warning (HDL Direct)
Description : WARNING(SPCOHD-22): The specified property: ATSAM3U1CB-AU = I2 was ignored for the instance: SPLIT_INST, PATH: true because two split properties are specified for the instance. Ensure that you specify either SPLIT_INST_NAME or SPLIT_INST for one instance.
Object dump:
{
page: 1
instance: I2
cell name: ATSAM3U1CB-AU
}
")
(location
(
(object_kind "Instance")
(canonical_name "_!drawerror inst I2;")
(parent_canonical_name "DRAWERROR INST I2")
(drawing_name "@usb2iterface_lib.sch(sch_1):page1")
)
)
)
(
(tool "HDL_Direct")
(class "SCHEMATIC")
(severity 30)
(error_num 3)
(short_msg "WARNING(SPCOHD-22): The specified property: ATSAM3U1CB-AU = I1 was ignored for the instance: SPLIT_INST, PATH: true because two split properties are specified for the instance. Ensure that you specify either SPLIT_INST_NAME or SPLIT_INST for one instance.")
(long_msg "Severity : Warning (HDL Direct)
Description : WARNING(SPCOHD-22): The specified property: ATSAM3U1CB-AU = I1 was ignored for the instance: SPLIT_INST, PATH: true because two split properties are specified for the instance. Ensure that you specify either SPLIT_INST_NAME or SPLIT_INST for one instance.
Object dump:
{
page: 1
instance: I1
cell name: ATSAM3U1CB-AU
}
")
(location
(
(object_kind "Instance")
(canonical_name "_!drawerror inst I1;")
(parent_canonical_name "DRAWERROR INST I1")
(drawing_name "@usb2iterface_lib.sch(sch_1):page1")
)
)
)
)
)

77
board/hdl/temp/sch.sch_1.mkr Normal file
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(marker_file
(version 1.0)
(markers
(
(tool "Concept")
(class "SCHEMATIC")
(severity 30)
(error_num 1)
(short_msg "WARNING(SPCOCD-22): The specified property: SPLIT_INST = true was ignored for the instance: atsam3u1cb-au, PATH: i3 because two split properties are specified for the instance. Ensure that you specify either SPLIT_INST_NAME or SPLIT_INST for one instance.")
(long_msg "Severity : Warning (Concept)
Description : WARNING(SPCOCD-22): The specified property: SPLIT_INST = true was ignored for the instance: atsam3u1cb-au, PATH: i3 because two split properties are specified for the instance. Ensure that you specify either SPLIT_INST_NAME or SPLIT_INST for one instance.
Object dump:
{
page: 1
instance: i3
cell name: atsam3u1cb-au
}
")
(location
(
(object_kind "Instance")
(canonical_name "_!drawerror inst i3;")
(parent_canonical_name "DRAWERROR INST i3")
(drawing_name "@usb2iterface_lib.sch(sch_1):page1")
)
)
)
(
(tool "Concept")
(class "SCHEMATIC")
(severity 30)
(error_num 2)
(short_msg "WARNING(SPCOCD-22): The specified property: SPLIT_INST = true was ignored for the instance: atsam3u1cb-au, PATH: i2 because two split properties are specified for the instance. Ensure that you specify either SPLIT_INST_NAME or SPLIT_INST for one instance.")
(long_msg "Severity : Warning (Concept)
Description : WARNING(SPCOCD-22): The specified property: SPLIT_INST = true was ignored for the instance: atsam3u1cb-au, PATH: i2 because two split properties are specified for the instance. Ensure that you specify either SPLIT_INST_NAME or SPLIT_INST for one instance.
Object dump:
{
page: 1
instance: i2
cell name: atsam3u1cb-au
}
")
(location
(
(object_kind "Instance")
(canonical_name "_!drawerror inst i2;")
(parent_canonical_name "DRAWERROR INST i2")
(drawing_name "@usb2iterface_lib.sch(sch_1):page1")
)
)
)
(
(tool "Concept")
(class "SCHEMATIC")
(severity 30)
(error_num 3)
(short_msg "WARNING(SPCOCD-22): The specified property: SPLIT_INST = true was ignored for the instance: atsam3u1cb-au, PATH: i1 because two split properties are specified for the instance. Ensure that you specify either SPLIT_INST_NAME or SPLIT_INST for one instance.")
(long_msg "Severity : Warning (Concept)
Description : WARNING(SPCOCD-22): The specified property: SPLIT_INST = true was ignored for the instance: atsam3u1cb-au, PATH: i1 because two split properties are specified for the instance. Ensure that you specify either SPLIT_INST_NAME or SPLIT_INST for one instance.
Object dump:
{
page: 1
instance: i1
cell name: atsam3u1cb-au
}
")
(location
(
(object_kind "Instance")
(canonical_name "_!drawerror inst i1;")
(parent_canonical_name "DRAWERROR INST i1")
(drawing_name "@usb2iterface_lib.sch(sch_1):page1")
)
)
)
)
)

18
board/hdl/temp/sessionlog.txt Normal file
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01/22/16 17:18:36 Opening project C:/Users/jyzhiyu/Dropbox/work/USB2SPDIF/board/hdl/usb2iterface.cpm
01/22/16 17:18:36 cdslib C:/Users/jyzhiyu/Dropbox/work/USB2SPDIF/board/hdl/cds.lib opened
01/22/16 17:18:36 Project C:/Users/jyzhiyu/Dropbox/work/USB2SPDIF/board/hdl/usb2iterface.cpm opened
01/22/16 17:18:40 Loading cell atsam3u1cb-au from library usb2iterface_lib
01/22/16 17:18:40 Loading view sym_3 of cell atsam3u1cb-au
01/22/16 17:18:40 Loading view sym_2 of cell atsam3u1cb-au
01/22/16 17:18:40 Loading view sym_1 of cell atsam3u1cb-au
01/22/16 17:18:40 Loading view chips of cell atsam3u1cb-au
01/22/16 17:18:40 Loading view entity of cell atsam3u1cb-au
01/22/16 17:18:40 Loading cell atsam3u1cb-au from library usb2iterface_lib
01/22/16 17:18:40 Analyzing view relationships of cell atsam3u1cb-au in library usb2iterface_lib
01/22/16 17:18:40 Completed loading cell atsam3u1cb-au from library usb2iterface_lib
01/22/16 17:18:40 Starting validations on cell atsam3u1cb-au of library usb2iterface_lib
01/22/16 17:18:40 Completed validations on cell atsam3u1cb-au of library usb2iterface_lib
01/22/16 17:19:50 Starting validations on cell atsam3u1cb-au of library usb2iterface_lib
01/22/16 17:19:50 Completed validations on cell atsam3u1cb-au of library usb2iterface_lib
01/22/16 17:19:51 Completed saving cell atsam3u1cb-au in library usb2iterface_lib
01/22/16 17:19:52 Project C:/Users/jyzhiyu/Dropbox/work/USB2SPDIF/board/hdl/usb2iterface.cpm is closed.

0
board/hdl/temp/van.log Normal file
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board/hdl/usb2iterface.cpm
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LOADING design file

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board/hdl/usb2iterface.log Normal file
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LIBRARY NAME: usb2iterface_lib
CELL NAME: atsam3u1cb-au
SPLBBK-5:Package 'ATSAM3U1CB-AU_SMT' : Pin numbers extracted from footprint lqfp100-p0_5.psm,Information

3
board/hdl/usb2iterface.rep Normal file
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LIBRARY NAME: usb2iterface_lib
CELL NAME: atsam3u1cb-au PASSED
Total Time taken: 1.560000 sec

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