27 lines
1.3 KiB
Plaintext
27 lines
1.3 KiB
Plaintext
HDL Direct 16.5-S048 (v16-5-13DK) 9/23/2013
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Copyright (C) 1996 Cadence Design Systems, Inc.
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Processing cell view: SCH(SCH_1)
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Generating for languages: Verilog
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Processing page 1
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WARNING(SPCOHD-22): The specified property: ATSAM3U1CB-AU = I3 was ignored for the instance: SPLIT_INST, PATH: true because two split properties are specified for the instance. Ensure that you specify either SPLIT_INST_NAME or SPLIT_INST for one instance.
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Object description:
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Page: 1 Instance: I3 Cell name: ATSAM3U1CB-AU
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WARNING(SPCOHD-22): The specified property: ATSAM3U1CB-AU = I2 was ignored for the instance: SPLIT_INST, PATH: true because two split properties are specified for the instance. Ensure that you specify either SPLIT_INST_NAME or SPLIT_INST for one instance.
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Object description:
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Page: 1 Instance: I2 Cell name: ATSAM3U1CB-AU
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WARNING(SPCOHD-22): The specified property: ATSAM3U1CB-AU = I1 was ignored for the instance: SPLIT_INST, PATH: true because two split properties are specified for the instance. Ensure that you specify either SPLIT_INST_NAME or SPLIT_INST for one instance.
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Object description:
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Page: 1 Instance: I1 Cell name: ATSAM3U1CB-AU
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Total number of pages: 1
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Generating Output File lib.cell:view usb2iterface_lib.sch:sch_1
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Design Entry HDL Direct: Created Netlist.
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