USB2SPDIF/board/hdl/worklib/sch/packaged/pxl.dbg.old
2016-01-26 19:49:42 +08:00

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Log File: C:\Users\jyzhiyu\AppData\Local\Temp\s2c0.
Markers File: C:\Users\jyzhiyu\AppData\Local\Temp\s2c0.1
Debug File: C:\Users\jyzhiyu\AppData\Local\Temp\s2c0.3
Debug[0] := TRUE
Elapsed time since start = (00:00:00)
**************************************************************
* End processing project file and command line (00:00:00) *
**************************************************************
*************************
* Loading State Files *
*************************
Elapsed time since start = (00:00:00)
*****************************************
* End loading State Files (00:00:00) *
*****************************************
****************************************
* Starting to assign physical parts. *
****************************************
Elapsed time since start = (00:00:00)
***********************************************
* End assigning physical parts. (00:00:00) *
***********************************************
***************
* Packaging *
***************
Elapsed time since start = (00:00:00)
*******************************
* End packaging (00:00:00) *
*******************************
DDB_INFO: State file for design SCH successfully written.
DDB_INFO: Pst files for design SCH successfully written.