176 lines
6.5 KiB
Plaintext
176 lines
6.5 KiB
Plaintext
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Cadence Design Systems, Inc.
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Packager-XL 16.5-S051 (v16-5-13DR) WIN32 1/6/2014 12:00:00 IST
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(C) Copyright 1994, Cadence Design Systems, Inc.
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Run on Mon Jan 25 15:51:37 2016
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**********************************************
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* Processing project file and command line *
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**********************************************
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ANNOTATE 'BODY' 'PIN'
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COMP_DEF_PROP 'ALT_SYMBOLS' 'JEDEC_TYPE' 'NC_PINS' 'MERGE_NC_PINS'
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'POWER_GROUP' 'POWER_PINS' 'MERGE_POWER_PINS' 'PINCOUNT'
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COMP_INST_PROP 'GROUP' 'ROOM' 'REUSE_INSTANCE' 'REUSE_ID' 'REUSE_NAME'
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'SIGNAL_MODEL' 'DEFAULT_SIGNAL_MODEL'
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'VOLT_TEMP_SIGNAL_MODEL' 'SYMBOL_EDITED'
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'INCLUDE_IN_RF_TOPOLOGY' 'NO_XNET_CONNECTION'
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'EMBEDDED_PLACEMENT' 'ISRFELEMENT' 'RFELEMENTTYPE' 'RFLAYER'
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'RFLAYER1' 'RFLAYER2' 'RFLAYER3' 'RFLAYER4' 'RFLAYER5'
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'RFLAYER6' 'RFLAYER7' 'RFLAYER8' 'RFLAYER9' 'RFLAYER10'
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'RFLAYER11' 'RFLAYER12' 'RFLAYER13' 'RFLAYER14' 'RFLAYER15'
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'RFLAYER16' 'RFCOUPLINGMODE' 'RFFLIPMODE' 'RFANGLE'
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'RFANGLE1' 'RFWIDTH' 'RFWIDTH1' 'RFWIDTH2' 'RFWIDTH3'
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'RFWIDTH4' 'RFWIDTH5' 'RFWIDTH6' 'RFWIDTH7' 'RFWIDTH8'
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'RFWIDTH9' 'RFWIDTH10' 'RFWIDTH11' 'RFWIDTH12' 'RFWIDTH13'
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'RFWIDTH14' 'RFWIDTH15' 'RFWIDTH16' 'RFLENGTH' 'RFLENGTH1'
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'RFLENGTH2' 'RFLENGTH3' 'RFLENGTH4' 'RFLENGTH5' 'RFLENGTH6'
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'RFLENGTH7' 'RFLENGTH8' 'RFSPACING' 'RFSPACING1'
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'RFSPACING2' 'RFSPACING3' 'RFSPACING4' 'RFSPACING5'
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'RFSPACING6' 'RFSPACING7' 'RFSPACING8' 'RFSPACING9'
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'RFSPACING10' 'RFSPACING11' 'RFSPACING12' 'RFSPACING13'
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'RFSPACING14' 'RFSPACING15' 'RFOFFSETX' 'RFOFFSETY'
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'RFRADIUS' 'RFDEPTH' 'RFFREQUENCY' 'RFMITERFRACTION'
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'RFBENDMODE' 'RFNUMBERLEGS' 'RFNUMBERPAIRS' 'RFNUMBERTURNS'
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'RFCAPACITANCE' 'RFRESISTANCE' 'RFINDUCTANCE'
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'RFPADSTACKNAME' 'RFPADSSMNAME1' 'RFPADSSMNAME2'
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'RFPADBEGINLAYER' 'RFPADENDLAYER' 'RFPADLINEWIDTH1'
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'RFPADLINEWIDTH2' 'RFPADDIAMETER1' 'RFPADDIAMETER2'
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'RFPADLENGTH1' 'RFPADLENGTH2' 'RFHOLEDIAMETER' 'RFPADANGLE'
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'RFDRANAME' 'RFPADTYPE' 'RFUID' 'RFBLOCK' 'RFDCNET'
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'CDS_FSP_LIB_PART_MODEL' 'CDS_FSP_IS_FPGA'
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'CDS_FSP_INSTANCE_NAME' 'CDS_FSP_INSTANCE_ID'
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SUPPRESS_GLOBAL_SHORT_CHECK OFF
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DEBUG 0
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DEFAULT_PHYS_DES_PREFIX U
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FEEDBACK 'OFF'
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MAX_ERRORS 999
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NET_NAME_CHARS @ - ! # % & ( ) * . / : ? [ ] ^ _ ` +
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= > 0 1 2 3 4 5 6 7 8 9
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NET_NAME_LENGTH 31
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NUM_OLD_VERSIONS 3
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OPTIMIZE OFF
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REUSE_REFDES ON
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OPF_OPTIMIZATION OFF
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HARD_LOC_SEC OFF
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FORCE_PTF_ENTRY OFF
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REGENERATE_PHYSICAL_NET_NAME OFF
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SCH_POWER_GROUP_WINS_OVER_PPT OFF
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NULL_OPT_VALID OFF
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USE_VECTOR_NOTATION ON
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FILTER_ECS_FROM_XNET ON
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OUTPUT 'ON'
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PACKAGE_PROP 'GROUP' 'ROOM'
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PART_TYPE_LENGTH 31
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REF_DES_LENGTH 31
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REPACKAGE OFF
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ELECTRICAL_CONSTRAINTS ON
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OVERWRITE_CONSTRAINTS OFF
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RUN_DIR ./worklib/sch/packaged/
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STRICT_PACKAGE_PROP 'REUSE_INSTANCE'
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USE_LIBRARY_PPT ON
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USE_STATE ON
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WARNINGS ON
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LIBRARY 'usb2iterface_lib' 'standard' 'connector' 'crystal_osc' 'diode'
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'discrete' 'disp' 'itead_standard_lib' 'logic' 'mcu' 'misc_ic'
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'module' 'motor' 'mtg' 'opamp' 'others' 'ram_flash' 'regulator'
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'relay' 'sensor' 'socket' 'sonic_socket' 'std' 'switch'
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'transformer' 'transistor'
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CDSPROP_FILE
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VIEW_PTF part_table
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VIEW_PACKAGER packaged
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VIEW_CONSTRAINTS sch_1
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DESIGN_LIBRARY usb2iterface_lib
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DESIGN_NAME sch
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VIEW_CONFIG_PHYSICAL cfg_package
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SD_SUFFIX_SEPARATOR _
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STOP_PST_GEN_ON_PTF_MISMATCH ON
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IGNORE_PRIM_BINDING OFF
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LOG_INST_PHYS_PATH ON
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ANNOTATE_VISIBLE_SEC OFF
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PTF_MISMATCH_EXCLUDE_INJ_PROP 'ALL'
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IMPORT_HFS_HARDSEC_ON_SWAP_PINS OFF
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ALLOW_PTFVALUE_INITIAL_BLANKS ON
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PRESERVE_UNSUBSTITUTED_MACROS OFF
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DETECT_SYS_NETSHORTS_PKG ON
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PROCESS_PIN_SHORT_PROP OFF
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STOP_PACKAGE_ON_SCHEMATIC_ERROR OFF
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LOCK_FILE_PERM 444
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LOCK_FOR_SAME_USER OFF
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ERROR_ON_MISMATCHED_INTERFACE ON
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RETAIN_ZERO_NODE_NETS OFF
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IGNORE_ERR_EMPTY_LONGPARTNAME OFF
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ERROR_ILLEGAL_QUOTE_PPT OFF
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B2F_OVERWRITE_CONSTRAINTS OFF
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CACHE_ENABLED OFF
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CACHE_NAME cache
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PTF_NAME cache
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**************************************************************
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* End processing project file and command line (00:00:00) *
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**************************************************************
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Creating Configuration "cfg_package" for Design "sch"
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INFO(SPCODD-181): Loading C:\Cadence\SPB_16.5\share\cdssetup\cdsprop.tmf.
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INFO(SPCODD-181): Loading C:\Cadence\SPB_16.5\share\cdssetup\cdsprop.paf.
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*********************************
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* Loading the design database *
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*********************************
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INFO(SPCODD-181): Loading Z:/logicsymbol/connector/usb_microf/part_table/part.~
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ptf.
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INFO(SPCODD-181): Loading Z:/logicsymbol/discrete/res/part_table/part.ptf.
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INFO(SPCODD-181): Loading Z:/logicsymbol/discrete/fb/part_table/part.ptf.
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INFO(SPCODD-181): Loading Z:/logicsymbol/discrete/cap/part_table/part.ptf.
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*************************
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* Loading State Files *
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*************************
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Loading ./worklib/sch/packaged/pxl.state.
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*****************************************
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* End loading State Files (00:00:00) *
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*****************************************
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****************************************
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* Starting to assign physical parts. *
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****************************************
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***********************************************
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* End assigning physical parts. (00:00:00) *
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***********************************************
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***************
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* Packaging *
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***************
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*******************************
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* End packaging (00:00:00) *
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*******************************
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INFO(SPCOPK-1442): No errors detected
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INFO(SPCOPK-1444): No warnings detected
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Start time 15:51:37
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End time 15:51:38
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Elapsed time 0:00:01
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***************************************************************************
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* Packager-XL execution done.
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***************************************************************************
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Starting to audit ECsets in the design...
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Audit completed successfully. |