23 lines
1.3 KiB
Plaintext
23 lines
1.3 KiB
Plaintext
\t (00:00:03) allegro 16.5 S057 (v16-5-13DL) i86
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\t (00:00:03) Journal start - Thu Feb 18 16:59:22 2016
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\t (00:00:03) Host=RD-ZHENGZHIYU User=jyzhiyu Pid=1956 CPUs=4
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\t (00:00:03)
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\t (00:00:04) Opening existing design...
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\w (00:00:04) WARNING(SPMHDB-214): Allegro PCB Design GXL (legacy) opening an Allegro XL design.
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\w (00:00:04) WARNING(SPMHDB-213): DRC set to "out of date". This product supports a different DRC set than last product used on drawing.
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\w (00:00:04) WARNING(SPMHOD-34): Design was last saved by lower capability product (Allegro XL). DRC is set out-of-date, you may wish to update DRC to reflect current rules.
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\i (00:00:18) fillin confirm
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\d (00:00:18) Database opened: C:/Users/jyzhiyu/Dropbox/work/USB2SPDIF/board/hdl/worklib/sch/physical/usb2interface.brd
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\i (00:00:19) trapsize 1086
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\i (00:00:19) trapsize 1043
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\i (00:00:19) trapsize 1090
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\i (00:00:19) trapsize 1044
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\i (00:00:19) trapsize 1044
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\i (00:00:19) generaledit
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\i (00:00:20) open
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\i (00:00:40) fillin "C:\Users\jyzhiyu\Desktop\wifiLed\worklib\wifi_led\physical\wifi_led2.brd"
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\i (00:00:40) cd "C:\Users\jyzhiyu\Desktop\wifiLed\worklib\wifi_led\physical"
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\t (00:00:40) Opening existing design...
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\i (00:00:40) trapsize 3071
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\t (00:00:40) Journal end - Thu Feb 18 16:59:59 2016
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