173 lines
8.3 KiB
C
173 lines
8.3 KiB
C
/*
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* Copyright (c) 2014, 2015 Benjamin Vernoux <bvernoux@airspy.com>
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*
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* This file is part of AirSpy.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; see the file COPYING. If not, write to
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* the Free Software Foundation, Inc., 51 Franklin Street,
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* Boston, MA 02110-1301, USA.
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*/
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#include "airspy_conf.h"
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/*
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WARNING PLL1 CONF for I2C0 & I2C1 from airspy_conf.h shall be modified,
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according to PLL1 High Speed Mode & PLL1 Low Speed Mode defined below
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*/
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/*
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Clock configuration with GP_CLKIN=20MHz
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Configuration of clocks at init (sys_clock_init())
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*/
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const airspy_sys_clock_t airspy_m4_init_conf =
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{
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/* Configure PLL0USB to produce 480MHz clock from GP_CLKIN */
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0x040E03FF, // uint32_t pll0_usb_mdiv;
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0x00000000, // uint32_t pll0_usb_npdiv;
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(PLL0USB_CTRL_FLAG_DIRECT_I | PLL0USB_CTRL_FLAG_DIRECT_O), // uint32_t pll0usb_ctrl_flags; DirectI=PLL0USB_CTRL_FLAG_DIRECT_I or/and DirectO=PLL0USB_CTRL_FLAG_DIRECT_O */
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/* PLL1 clock from GP_CLKIN */
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/* Packing Enabled:
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PLL1 High Speed Mode Set PLL1 to 20MHz * (8+1) = 180MHz
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No Packing:
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PLL1 High Speed Mode Set PLL1 to 20MHz * (6+1) = 140MHz */
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{
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0, // uint32_t pll1_hs_psel;
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0, // uint32_t pll1_hs_nsel;
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6, // uint32_t pll1_hs_msel;
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},
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/* PLL1 Low Speed Mode => Set PLL1 to 20MHz * (1+1) = 40MHz */
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{
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0, // uint32_t pll1_ls_psel;
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0, // uint32_t pll1_ls_nsel;
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1, // uint32_t pll1_ls_msel;
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}
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};
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/*
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SampleRate configuration with GP_CLKIN=20MHz
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Configuration of PLL0AUDIO shall not exceed 80MHz for ADCHS
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For PLL0AUDIO sys_clock_samplerate() set SEL_EXT to 1 => MDEC enabled. Fractional divider not used.
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For PLL0AUDIO see UM10503 Rev1.8 "Fig 34. PLL0 with fractional divider" Page 184 / 1420 for more details.
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Configuration of IDIVB => Integer divider B divider values (1/(IDIV + 1))
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*/
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const airspy_sys_samplerate_t airspy_m4_conf[AIRSPY_CONF_NB] =
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{
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/* Conf 0 => AIRSPY_SAMPLERATE_10MSPS = 0 => airspy_samplerate_t
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CGU_SRC_GP_CLKIN=20MHz from SI5351C CLK7 LPC4370 GP_CLKIN (see airspy_m4_init_conf)
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*/
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{
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/* PLL0AUDIO */
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0x00000000, // uint32_t pll0audio_mdiv;
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0x00000000, // uint32_t pll0audio_npdiv;
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0x00000000, // uint32_t pll0audio_ctrl_flags; DirectI=PLL0AUDIO_CTRL_FLAG_DIRECT_I or/and DirectO=PLL0AUDIO_CTRL_FLAG_DIRECT_O */
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/* IDIVB (from GP_CLKIN) */
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0, // uint8_t adchs_idivb; /* 0 to 15 (0 means direct connection GP_CLKIN to ADCHS_CLK) */
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{ 0, 0, 0 } /* uint8_t padding[3] */
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},
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/* Conf 1 => AIRSPY_SAMPLERATE_2_5MSPS = 1 */
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{
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/* PLL0AUDIO */
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0x00000000, // uint32_t pll0audio_mdiv;
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0x00000000, // uint32_t pll0audio_npdiv;
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0x00000000, // uint32_t pll0audio_ctrl_flags; DirectI=PLL0AUDIO_CTRL_FLAG_DIRECT_I or/and DirectO=PLL0AUDIO_CTRL_FLAG_DIRECT_O */
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/* IDIVB not used set it to 0 */
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3, // uint8_t adchs_idivb; /* 0 to 15 (0 means direct connection GP_CLKIN to ADCHS_CLK) */
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{ 0, 0, 0 } /* uint8_t padding[3] */
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}
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};
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uint8_t si5351c_config[2][180] =
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{
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/* Conf 0 XTAL 25MHZ CLK */
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{
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#ifdef AIRSPY_NOS
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/* Respective value for register 0 to register 180
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Options->Save device registers (not for factory programming)
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See file Si5351C-AIRSPY_NOS-GM_LPC_20MHz_R820T_20MHz_0pf_New_FULL_NotFactory.txt
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SI5351C Configuration details (XTAL 25MHz):
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Channel 0 = 20MHz R820T (Drive Strength 6mA, Inverted)
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Channel 1 = 32768Hz LPC4370 RTC (Drive Strength 2mA)
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Channel 2 to 6 = Disabled/Not Used
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Channel 7 = 20MHz LPC4370 (Drive Strength 8mA)
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*/
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0x00, 0x00, 0x18, 0x00, 0x00, 0x00, 0x8F, 0x01, 0x00, 0x00, // 0 - 9
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7E, 0x83, 0x83, 0x83, // 10 - 19
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0x83, 0x83, 0x83, 0x4F, 0x00, 0x00, 0x00, 0x05, 0x00, 0x0F, // 20 - 29
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0x99, 0x00, 0x00, 0x03, 0x00, 0x01, 0x00, 0x0E, 0x00, 0x00, // 30 - 39
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0x00, 0x00, 0x00, 0x01, 0x00, 0x12, 0x00, 0x00, 0x00, 0x00, // 40 - 49
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 50 - 59
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 60 - 69
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 70 - 79
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 80 - 89
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0x00, 0x2C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 90 - 99
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 100 - 109
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 110 - 119
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 120 - 129
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 130 - 139
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 140 - 149
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 150 - 159
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 160 - 169
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 // 170 - 179
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#else /* AIRSPY One/Demo */
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/* Respective value for register 0 to register 180
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Options->Save device registers (not for factory programming)
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See file Si5351C-AIRSPY_NOS-GM_LPC_20MHz_R820T_20MHz_0pf_New_FULL_NotFactory.txt
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SI5351C Configuration details (XTAL 25MHz):
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Channel 0 = 20MHz R820T (Drive Strength 2mA)
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Channel 1 = 32768Hz LPC4370 RTC (Drive Strength 2mA)
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Channel 2 to 6 = Disabled/Not Used
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Channel 7 = 20MHz LPC4370 (Drive Strength 2mA)
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*/
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0x00, 0x00, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 0 - 9
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x6C, 0x2C, 0x83, 0x83, // 10 - 19
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0x83, 0x83, 0x83, 0x4C, 0x00, 0x00, 0x00, 0x05, 0x00, 0x0F, // 20 - 29
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0x99, 0x00, 0x00, 0x03, 0x00, 0x01, 0x00, 0x0A, 0x00, 0x00, // 30 - 39
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0x00, 0x00, 0x00, 0x01, 0x00, 0x0D, 0x00, 0x00, 0x00, 0x00, // 40 - 49
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0x04, 0x00, 0x42, 0x3A, 0x34, 0x00, 0x01, 0x80, 0x00, 0x00, // 50 - 59
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 60 - 69
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 70 - 79
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 80 - 89
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0x00, 0x2C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 90 - 99
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 100 - 109
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 110 - 119
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 120 - 129
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 130 - 139
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 140 - 149
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 150 - 159
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 160 - 169
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 170 - 179
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#endif
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},
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/* Conf 1 AIRSPY_NOS CLKIN 10MHz CLK */
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{
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0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x8F, 0x01, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x0C, 0x7E, 0x2C, 0x87, 0x87,
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0x87, 0x87, 0xC7, 0x4F, 0x00, 0x00, 0x00, 0x01, 0x00, 0x2A,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x20, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x01, 0x00, 0x0F, 0x00, 0x00, 0x00, 0x00,
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0x04, 0x00, 0x42, 0x86, 0x7F, 0x00, 0x02, 0x80, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x2C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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}
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};
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