59 lines
2.6 KiB
Plaintext
59 lines
2.6 KiB
Plaintext
/*
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* Copyright 2012 Michael Ossmann <mike@ossmann.com>
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* Copyright 2012 Jared Boone <jared@sharebrained.com>
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* Copyright 2013 Benjamin Vernoux <bvernoux@gmail.com>
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*
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* This file is part of AirSpy (based on HackRF project).
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; see the file COPYING. If not, write to
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* the Free Software Foundation, Inc., 51 Franklin Street,
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* Boston, MA 02110-1301, USA.
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*/
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/* Linker script for AirSpy (LPC4370, 1M or 4MB SPI flash, 282K SRAM). */
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MEMORY
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{
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/* rom is really the shadow region that points to SPI flash or elsewhere */
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rom (rx) : ORIGIN = 0x00000000, LENGTH = 1M
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ram_local1 (rwx) : ORIGIN = 0x10000000, LENGTH = 128K
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ram_local2 (rwx) : ORIGIN = 0x10080000, LENGTH = 72K
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/* LPC437x only: Reserved for M0 subsystem SRAM 16KB + 2KB */
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ram_local_m0sub (rwx) : ORIGIN = 0x18000000, LENGTH = 18K
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ram_ahb1 (rwx) : ORIGIN = 0x20000000, LENGTH = 7K
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ram_ahb1_m4_share (rwx) : ORIGIN = 0x20001C00, LENGTH = 1K
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ram_ahb1_adchs (rwx) : ORIGIN = 0x20002000, LENGTH = 4K
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ram_ahb1_m0_share (rwx) : ORIGIN = 0x20003000, LENGTH = 4K
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/* Removed 32K of AHB SRAM for USB buffer. Straddles two blocks of RAM
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* to get performance benefit of having two USB buffers addressable
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* simultaneously (on two different buses of the AHB multilayer matrix)
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*/
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/* ram_ahb1_0 (rwx) : ORIGIN = 0x20004000, LENGTH = 16K */
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/* ram_ahb1_1 (rwx) : ORIGIN = 0x20008000, LENGTH = 16K */
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/* Reserved for Cortex M0 code/data */
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ram_ahb2 (rwx) : ORIGIN = 0x2000C000, LENGTH = 16K
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}
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cm4_data_share = ORIGIN(ram_ahb1_m4_share); /* M4 data shared (write by M4 read by M0 */
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adchs_data = ORIGIN(ram_ahb1_adchs); /* M4 ADCHS data (write by ADCHS DMA or M4) */
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cm0_data_share = ORIGIN(ram_ahb1_m0_share); /* M0 data shared (write by M0 read by M4) */
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cm0_exec_baseaddr = ORIGIN(ram_ahb2); /* Used by M4 to load code from M4 RAM to M0 final exec/run addr */
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cm0s_exec_baseaddr = ORIGIN(ram_local_m0sub); /* Used by M4 to load code from M4 RAM to M0Sub final exec/run addr */
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/* Include the common ld script. */
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INCLUDE libopencm3_lpc43xx.ld
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