105 lines
3.1 KiB
C
105 lines
3.1 KiB
C
/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2012/2014 Benjamin Vernoux <bvernoux@gmail.com>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <libopencm3/lpc43xx/ipc.h>
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#include <libopencm3/lpc43xx/creg.h>
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#include <libopencm3/lpc43xx/rgu.h>
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/* Set M0 in reset mode */
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void ipc_halt_m0(void)
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{
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volatile uint32_t rst_active_status1;
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/* Check if M0 is reset by reading status */
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rst_active_status1 = RESET_ACTIVE_STATUS1;
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/* If the M0 has reset not asserted, halt it... */
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while (rst_active_status1 & RESET_CTRL1_M0APP_RST) {
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RESET_CTRL1 = ((~rst_active_status1) | RESET_CTRL1_M0APP_RST);
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rst_active_status1 = RESET_ACTIVE_STATUS1;
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}
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}
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/* Start M0 */
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void ipc_start_m0(uint32_t cm0_baseaddr)
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{
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volatile uint32_t rst_active_status1;
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/* Set M0 memory mapping to point to start of M0 image */
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CREG_M0APPMEMMAP = cm0_baseaddr;
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/* Start/run M0 core */
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/* Release Slave from reset, first read status */
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rst_active_status1 = RESET_ACTIVE_STATUS1;
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/* If the M0 is being held in reset, release it */
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/* 1 = no reset, 0 = reset */
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while (!(rst_active_status1 & RESET_CTRL1_M0APP_RST)) {
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RESET_CTRL1 = ((~rst_active_status1) & ~RESET_CTRL1_M0APP_RST);
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rst_active_status1 = RESET_ACTIVE_STATUS1;
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}
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}
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/* Clear event M0 */
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void ipc_m0apptxevent_clear(void) {
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CREG_M0TXEVENT &= ~CREG_M0TXEVENT_TXEVCLR;
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}
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/* Set M0s in reset mode (only for LPC4370) */
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void ipc_halt_m0s(void)
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{
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volatile uint32_t rst_active_status0;
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/* Check if M0s is reset by reading status */
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rst_active_status0 = RESET_ACTIVE_STATUS0;
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/* If the M0s has reset not asserted, halt it... */
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while (rst_active_status0 & RESET_CTRL0_M0_SUB_RST) {
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RESET_CTRL0 = ((~rst_active_status0) | RESET_CTRL0_M0_SUB_RST);
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rst_active_status0 = RESET_ACTIVE_STATUS0;
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}
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}
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/* Start M0s (only for LPC4370) */
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void ipc_start_m0s(uint32_t cm0s_baseaddr)
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{
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volatile uint32_t rst_active_status0;
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/* Set M0s memory mapping to point to start of M0 image */
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CREG_M0SUBMEMMAP = cm0s_baseaddr;
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/* Start/run M0s core */
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/* Release Slave from reset, first read status */
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rst_active_status0 = RESET_ACTIVE_STATUS0;
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/* If the M0 is being held in reset, release it */
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/* 1 = no reset, 0 = reset */
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while (!(rst_active_status0 & RESET_CTRL0_M0_SUB_RST)) {
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RESET_CTRL0 = ((~rst_active_status0) & ~RESET_CTRL0_M0_SUB_RST);
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rst_active_status0 = RESET_ACTIVE_STATUS0;
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}
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}
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/* Clear event M0s (only for LPC4370) */
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void ipc_m0subtxevent_clear(void) {
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CREG_M0SUBTXEVENT &= ~CREG_M0SUBTXEVENT_TXEVCLR;
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}
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