Kasli/ClockRecovery.Harness
Paweł 8ee3f96317 - Switched pullup resistors ( closes #46 )
- Switched TCA9517 to PCA9306 for truer 0V low level on I2C bus (both near FPGA and near FTDI)
- Removed EN pullup on IC13, increased pulldown strength on EN IC22
- Added PWM control for fan (+2 pins for fan) ( closes #44 )
- Extended PCB to fit 4 additional EEM connectors ( closes #11 )
- Placed SATA connector above SFP cage ( closes #29 )
- Moved JTAG connector to no longer collide with MMCX connector ( closes #23 )
- Moved SMA connector ( closes #33 )
- Switched level translator for a transistor (watch out for logic inversion)
- Added pullups/downs on Si549 and ADCLK948 (by default Si5324 is chosen on ADCLK948 and Si549 outputs are disabled) + pads for other option
- Removed DNP text, PDF schematics now show DNPed parts as crossed out
- Switched P5V0 _CLK buck to one with 1A output, added second LT3045 ( cf #40 )
- Updated power budget
2019-09-19 17:24:56 +02:00

2 lines
110 B
Plaintext

CDR_PLL_CTRL=Main_DCXO_SDA,Main_DCXO_SCL,Main_DCXO_OE,Helper_DCXO_OE,CLK_SEL,Helper_DCXO_SDA,Helper_DCXO_SCL