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New Design Review gitified_old_clb_svn/fw/CLBv2_Design/aes
History
peterj.nikhef.nl 42287e2f84 Solved TDC-tilt after configuration issue (http://elog.km3net.de/Electronics/149)
2015-06-23 09:44:39 +00:00
..
ip_cores
added aes test design to the clbv2_design folder
2014-02-03 15:26:33 +00:00
modules
Solved TDC-tilt after configuration issue (http://elog.km3net.de/Electronics/149)
2015-06-23 09:44:39 +00:00
sim
modified aes behaviour when no signal is present. Data are sent only when the locked signal is 1
2014-09-16 09:48:06 +00:00
syn
added missing files
2014-04-17 12:50:55 +00:00
top
added missing files
2014-04-17 12:50:55 +00:00
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