peterj.nikhef.nl a35ebf68ee Updated ease designs to contain the (hardware) watchdog implementation

2016-08-26 15:48:05 +00:00

..

mem2ldr.tcl

modified modelsim scripts

2013-08-15 15:35:01 +00:00

modelsim.ini

added a level of hierarchy for clb_wrpc. The pll that creates clk_sys_i is put one level up since the output of this pll is needed in the rest of the CLB.

2013-09-06 14:13:07 +00:00

Questa Sim_10.2a.lnk

modified modelsim scripts

2013-08-15 15:35:01 +00:00

VCom_Backannotated.tcl

This is the clb_wrpc design such as it is used to bugfix in wr_endpoint.vhd due to

2013-11-07 14:37:16 +00:00

VCom_Functional.tcl

Updated ease designs to contain the (hardware) watchdog implementation

2016-08-26 15:48:05 +00:00

vlog.opt

added a level of hierarchy for clb_wrpc. The pll that creates clk_sys_i is put one level up since the output of this pll is needed in the rest of the CLB.

2013-09-06 14:13:07 +00:00

VSim_Backannotated.tcl

This is the clb_wrpc design such as it is used to bugfix in wr_endpoint.vhd due to

2013-11-07 14:37:16 +00:00

VSim_Checkpoint.tcl

this set is based on the new wrpc files. the timing servo still sticks at SYNC_NSEC (but this can be due to old, non matching software).

2013-08-30 13:27:12 +00:00

VSim_Current_Revision.tcl

modified modelsim scripts

2013-08-15 15:35:01 +00:00

VSim_Functional.tcl

renamed clb_wrpc_top to clb_wrpc and clb_wrpc_top_tb clb_wrpc_tb

2013-10-01 09:38:43 +00:00

VSim_Restore.tcl

this set is based on the new wrpc files. the timing servo still sticks at SYNC_NSEC (but this can be due to old, non matching software).

2013-08-30 13:27:12 +00:00

wave_backannotated.tcl

This is the clb_wrpc design such as it is used to bugfix in wr_endpoint.vhd due to

2013-11-07 14:37:16 +00:00

wave.tcl

This is the clb_wrpc design such as it is used to bugfix in wr_endpoint.vhd due to

2013-11-07 14:37:16 +00:00