You've already forked gitified_old_clb_svn
87 lines
2.9 KiB
VHDL
87 lines
2.9 KiB
VHDL
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--
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-- This VHDL file was generated by EASE/HDL 7.4 Revision 9 from HDL Works B.V.
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--
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-- Ease library : design
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-- HDL library : work
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-- Host name : SERING
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-- User name : peterj
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-- Time stamp : Mon Nov 11 09:33:28 2013
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--
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-- Designed by :
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-- Company : HDL Works
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-- Project info :
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--
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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-- Object : Entity design.ClkDist
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-- Last modified : Mon Nov 11 09:33:27 2013.
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--------------------------------------------------------------------------------
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library ieee, work;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.EMAC16bit_Package.all;
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use work.v_array_package.all;
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entity ClkDist is
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port(
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ref_clk_62_5 : in std_logic;
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clk_sys_i : in std_logic;
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Emptyi : in std_logic_vector(NUM_UDP_PRTS-1 downto 0);
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Emptyo : out std_logic_vector(NUM_UDP_PRTS-1 downto 0);
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Fulli : in std_logic_vector(NUM_UDP_PRTS-1 downto 0);
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Fullo : out std_logic_vector(NUM_UDP_PRTS-1 downto 0);
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RdClk : out std_logic_vector(NUM_UDP_PRTS downto 0);
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RdReqi : in std_logic_vector(NUM_UDP_PRTS-1 downto 0);
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RdReqo : out std_logic_vector(NUM_UDP_PRTS-1 downto 0);
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Rx : in dbus_type_array(NUM_UDP_PRTS-1 downto 0);
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Tx : out dbus_type_array(NUM_UDP_PRTS-1 downto 0);
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UDP_Rx : out dbus_type_array(NUM_UDP_PRTS-1 downto 0);
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UDP_Tx : in dbus_type_array(NUM_UDP_PRTS-1 downto 0);
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WrClk : out std_logic_vector(NUM_UDP_PRTS-1 downto 0);
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WrReqi : in std_logic_vector(NUM_UDP_PRTS-1 downto 0);
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WrReqo : out std_logic_vector(NUM_UDP_PRTS-1 downto 0));
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end entity ClkDist;
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--------------------------------------------------------------------------------
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-- Object : Architecture design.ClkDist.rtl
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-- Last modified : Mon Nov 11 09:33:27 2013.
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--------------------------------------------------------------------------------
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architecture rtl of ClkDist is
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begin
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-- The RdClk and WrClk signals are assigned here.
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-- This creates one delta delay in simulation!
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-- In order to keep clock and data signals alligned all signals
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-- are simply fed forward (although also adding one delta delay).
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-- RX side
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Emptyo <= Emptyi;
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RdReqo <= RdReqi;
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UDP_Rx <= Rx;
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RdClk(0) <= ref_clk_62_5;
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RdClk(1) <= ref_clk_62_5;
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RdClk(2) <= clk_sys_i;
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RdClk(3) <= clk_sys_i;
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RdClk(4) <= clk_sys_i; -- The Fifo connected to the CPU which is running on 62,5 MHz
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-- Tx Side
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Fullo <= Fulli;
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WrReqo <= WrReqi;
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Tx <= UDP_Tx;
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WrClk(0) <= ref_clk_62_5;
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WrClk(1) <= ref_clk_62_5;
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WrClk(2) <= clk_sys_i;
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WrClk(3) <= clk_sys_i;
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end architecture rtl ; -- of ClkDist
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