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496ca2faac
LM32_2nd GPIO now 16 bits wide; used GPIO(8) to enable (or default disable to reduce interference) the test pad drivers (PPS and REF_CLK).
58 lines
1.5 KiB
VHDL
58 lines
1.5 KiB
VHDL
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--
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-- This VHDL file was generated by EASE/HDL 8.0 Revision 6 from HDL Works B.V.
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--
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-- Ease library : design
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-- HDL library : work
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-- Host name : SERING
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-- User name : peterj
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-- Time stamp : Fri Aug 01 11:18:08 2014
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--
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-- Designed by :
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-- Company : HDL Works
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-- Project info :
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--
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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-- Object : Entity design.Reg1en
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-- Last modified : Fri Mar 30 11:53:18 2012.
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--------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity Reg1en is
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port (
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Clk : in std_logic;
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D : in std_logic;
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En : in std_logic;
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Q : out std_logic;
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Rst : in std_logic);
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end entity Reg1en;
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-- Object : Architecture design.Reg1en.a0
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-- Last modified : Fri Mar 30 11:53:18 2012.
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--------------------------------------------------------------------------------
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architecture a0 of Reg1en is
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begin
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Process (Clk, Rst)
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Begin
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If Rst = '1' Then
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Q <= '0';
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ElsIf Rising_Edge(Clk) Then
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If En = '1' Then
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Q <= D;
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End If;
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End If;
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End Process;
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end architecture a0 ; -- of Reg1en
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