peterj.nikhef.nl 2c7ebd9a93 FPGA Corruption NRB (a.k.a LM32_2nd ROM bitflip issue); added (static) DPRAM buserr monitor IRQ; added ref_clk_lock synchronization FF's; re-ordered MCH states (VETO Status); added LVDS pullup/down.

2019-07-19 07:26:59 +00:00

..

stmach_master_top.vhd

New register added in the state machine with the number of events in supertime FIFO of TDCs and AES.

2018-07-31 07:06:30 +00:00

stmach_pkg.vhd

Incorporated the StMachine files (now including the monitoring channel) in the top level design. Note that EASE had problems defining port UDP_Tx: dbus_type_array(STM_UDP_PRTS-1 downto 0). This seems to be a bug. For the time being this need to be manually edited (it is already in place in fpga.vhd). Also made some improvements in the state machine files (now using a function to output a std_logic_vector when an ASCII string is input.

2014-08-12 16:02:48 +00:00

wb_stmach_master.vhd

New IRQ implementation for TDC FIFOS using the almost full flag

2016-03-29 11:43:43 +00:00

wrapped_stmach.vhd

FPGA Corruption NRB (a.k.a LM32_2nd ROM bitflip issue); added (static) DPRAM buserr monitor IRQ; added ref_clk_lock synchronization FF's; re-ordered MCH states (VETO Status); added LVDS pullup/down.

2019-07-19 07:26:59 +00:00