Logo
Explore
Sign In
NoIndexTests/gitified_old_clb_svn
0
Fork 0
You've already forked gitified_old_clb_svn
Files Issues Design Reviews Releases
Files
master
New Design Review gitified_old_clb_svn/fw/CLBv2_Design/tdc/modules
History
dacaldia 8f35ea864a min_tot vector reduced from 31 to 7 bits in DRU
2020-08-05 08:06:17 +00:00
..
ip_cores
small change in tdc_top due to QuestaSim Error: Actual expression (prefix expression) of formal "CLKB"/"OCLKB" is not globally static
2014-04-07 10:45:56 +00:00
DRU.vhd
min_tot vector reduced from 31 to 7 bits in DRU
2020-08-05 08:06:17 +00:00
mux_tdc.vhd
New minimum ToT functionality
2020-06-02 18:08:02 +00:00
tdc_fifo.vhd
Timing violation on RST of TDC frontend fifo's. Removed combinatorial OR. Ran do_xilinx.cmd => new bitfile
2018-10-19 13:12:10 +00:00
tdc_master_top.vhd
New minimum ToT functionality
2020-06-02 18:08:02 +00:00
tdc_pkg.vhd
New IRQ implementation for TDC FIFOS using the almost full flag
2016-03-29 11:43:43 +00:00
tdc_top.vhd
min_tot vector reduced from 31 to 7 bits in DRU
2020-08-05 08:06:17 +00:00
wb_tdc_master.vhd
new IRQ fifo full implementation removing test signals
2016-03-30 17:09:03 +00:00
Powered by AllSpice
English
Bahasa Indonesia Deutsch English Español Français Gaeilge Italiano Latviešu Magyar nyelv Nederlands Polski Português de Portugal Português do Brasil Suomi Svenska Türkçe Čeština Ελληνικά Български Русский Українська فارسی മലയാളം 日本語 简体中文 繁體中文(台灣) 繁體中文(香港) 한국어
JavaScript Licenses API Privacy Policy