You've already forked gitified_old_clb_svn
1939 lines
60 KiB
VHDL
1939 lines
60 KiB
VHDL
--------------------------------------------------------------------------------
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--
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-- This VHDL file was generated by EASE/HDL 7.4 Revision 9 from HDL Works B.V.
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--
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-- Ease library : work
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-- HDL library : work
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-- Host name : SERING
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-- User name : peterj
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-- Time stamp : Fri Sep 20 13:26:44 2013
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--
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-- Designed by :
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-- Company : HDL Works
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-- Project info :
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--
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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-- Object : Entity work.low
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-- Last modified : Fri Jul 05 14:23:51 2013.
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--------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.std_logic_unsigned.all;
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entity low is
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generic(
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n : integer := 8);
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port(
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o : out std_logic_vector(n-1 downto 0));
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end entity low;
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--------------------------------------------------------------------------------
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-- Object : Architecture work.low.structure
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-- Last modified : Fri Jul 05 14:23:51 2013.
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--------------------------------------------------------------------------------
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architecture structure of low is
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begin
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o <= (others => '0');
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end architecture structure ; -- of low
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--------------------------------------------------------------------------------
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-- Object : Entity work.dummy_tdc
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-- Last modified : Thu Jul 25 10:01:05 2013.
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--------------------------------------------------------------------------------
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library ieee, work;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.std_logic_unsigned.all;
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use work.tdc_pkg.all;
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entity dummy_tdc is
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port(
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tdc_i : out t_tdc_in);
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end entity dummy_tdc;
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--------------------------------------------------------------------------------
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-- Object : Architecture work.dummy_tdc.rtl
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-- Last modified : Thu Jul 25 10:01:05 2013.
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--------------------------------------------------------------------------------
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architecture rtl of dummy_tdc is
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begin
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-- tdc_i.clk_p <= '0';
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-- tdc_i.clk_n <= '1';
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tdc_i.s <= (others => '0');
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tdc_i.s_n <= (others => '1');
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tdc_i.sw <= '0';
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tdc_i.ss2 <= '0';
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end architecture rtl ; -- of dummy_tdc
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--------------------------------------------------------------------------------
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-- Object : Entity work.dummy_aes
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-- Last modified : Mon Jul 01 11:54:44 2013.
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--------------------------------------------------------------------------------
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library ieee, work;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.std_logic_unsigned.all;
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use work.aes_pkg.all;
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entity dummy_aes is
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port(
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aes_i : out t_aes_in);
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end entity dummy_aes;
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--------------------------------------------------------------------------------
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-- Object : Architecture work.dummy_aes.rtl
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-- Last modified : Mon Jul 01 11:54:44 2013.
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--------------------------------------------------------------------------------
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architecture rtl of dummy_aes is
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begin
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aes_i.audio_in <= '0';
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aes_i.fifo_rd <= '0';
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end architecture rtl ; -- of dummy_aes
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--------------------------------------------------------------------------------
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-- Object : Entity work.dummy_susm
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-- Last modified : Tue Sep 24 16:37:56 2013.
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--------------------------------------------------------------------------------
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library ieee, work;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.std_logic_unsigned.all;
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use work.susm_pkg.all;
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entity dummy_susm is
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port(
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clk_i : in std_logic;
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rst_i : in std_logic;
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aes_fifo_rd : out std_logic;
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aes_fifo_dout : in std_logic_vector(63 downto 0); -- data from decoded audio fifo
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aes_fifo_full : in std_logic; -- decoded audio fifo full
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aes_fifo_empty : in std_logic; -- decoded audio fifo empty
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susm_i : out t_susm_in;
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susm_o : in t_susm_out);
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end entity dummy_susm;
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--------------------------------------------------------------------------------
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-- Object : Architecture work.dummy_susm.rtl
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-- Last modified : Tue Sep 24 16:38:50 2013.
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--------------------------------------------------------------------------------
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architecture rtl of dummy_susm is
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COMPONENT dummy_susm_aes_fifo
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PORT (
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clk : IN STD_LOGIC;
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rst : IN STD_LOGIC;
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din : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
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wr_en : IN STD_LOGIC;
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rd_en : IN STD_LOGIC;
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dout : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
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full : OUT STD_LOGIC;
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empty : OUT STD_LOGIC
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);
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END COMPONENT;
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--signal counter : std_logic_vector(23 downto 0);
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--signal myvar : std_logic_vector(23 downto 0);
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signal tdccounter : std_logic_vector(23 downto 0);
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--signal aeswordcnt : std_logic_vector(1 downto 0);
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signal tdcwordcnt : std_logic_vector(1 downto 0);
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signal tmp_buf : std_logic_vector(47 downto 0);
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signal step : std_logic_vector(1 downto 0);
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signal myfifo_full, myfifo_empty : std_logic;
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signal myfifo_din : std_logic_vector(15 downto 0);
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signal myfifo_wren : std_logic;
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type fsm_t is (idle, read_status, wait_status, write_status);
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signal fsm : fsm_t;
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begin
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--aes: conversion between 64 bit fifo and 16 bit fifo
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dummy_susm_aes_fifo_inst : dummy_susm_aes_fifo
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PORT MAP (
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clk => clk_i,
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rst => rst_i,
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din => myfifo_din,
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wr_en => myfifo_wren,
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rd_en => susm_o.hydro_fifo_read_en,
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dout => susm_i.hydro_fifo_data,
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full => myfifo_full,
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empty => myfifo_empty
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);
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susm_i.hydro_fifo_full <= myfifo_full;
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susm_i.hydro_fifo_empty <= myfifo_empty;
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fsm_proc : process(clk_i)
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-- variable step : std_logic_vector(1 downto 0);
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begin
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if rising_edge(clk_i) then
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aes_fifo_rd <= '0';
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myfifo_wren <= '0';
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if rst_i = '1' then
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fsm <= idle;
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step <= (others => '0');
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else
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case fsm is
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when idle =>
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if aes_fifo_empty = '0' and myfifo_empty = '1' then
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-- data to be written
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fsm <= read_status;
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step <= (others => '0');
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end if;
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when read_status =>
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aes_fifo_rd <= '1';
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fsm <= wait_status;
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when wait_status =>
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fsm <= write_status;
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when write_status =>
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myfifo_wren <= '1';
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case step is
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when "00" =>
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myfifo_din <= aes_fifo_dout(63 downto 48);
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tmp_buf <= aes_fifo_dout(47 downto 0);
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step <= "01";
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when "01" =>
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myfifo_din <= tmp_buf(47 downto 32);
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step <= "10";
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when "10" =>
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myfifo_din <= tmp_buf(31 downto 16);
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step <= "11";
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when "11" =>
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myfifo_din <= tmp_buf(15 downto 0);
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step <= "00";
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fsm <= idle;
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when others =>
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fsm <= idle;
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end case;
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end case;
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end if;
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end if;
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end process;
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-- tdc simulation
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count_process :process(clk_i)
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begin
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if clk_i = '1' and clk_i'event then
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-- susm_i.hydro_fifo_data <= (others => '0');
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susm_i.tdc_fifo_data <= (others => '0');
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-- myvar <= counter + x"123456";
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if rst_i = '1' then
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-- counter <= (others => '0');
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tdccounter <= (others => '0');
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-- aeswordcnt <= (others => '0');
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tdcwordcnt <= (others => '0');
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else
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-- if (susm_o.hydro_fifo_read_en = '1') then
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-- --increment the part counter of a word
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-- aeswordcnt <= aeswordcnt + 1;
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--
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-- case aeswordcnt is
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-- when "00" =>
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-- -- first part of word
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-- susm_i.hydro_fifo_data(15) <= '0';
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-- susm_i.hydro_fifo_data(14 downto 8) <= counter (6 downto 0);
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-- susm_i.hydro_fifo_data(7) <= '1';
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-- susm_i.hydro_fifo_data(6 downto 0) <= counter (6 downto 0);
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-- when "01" =>
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-- -- second part of word
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-- susm_i.hydro_fifo_data(15 downto 0) <= counter(23 downto 8);
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-- when "10" =>
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-- -- third part of word
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-- susm_i.hydro_fifo_data(15 downto 8) <= counter(7 downto 0);
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-- susm_i.hydro_fifo_data(7 downto 0) <= myvar(23 downto 16); -- counter + x"123456";
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-- when "11" =>
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-- -- last part of word
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-- counter <= counter+'1';
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-- susm_i.hydro_fifo_data(15 downto 0) <= myvar(15 downto 0); -- counter + x"123456";
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-- when others =>
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-- aeswordcnt <= (others => '0');
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-- end case;
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-- end if;
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if (susm_o.tdc_fifo_read_en = '1') then
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--increment the part counter of a word
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tdcwordcnt <= tdcwordcnt + 1;
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case tdcwordcnt is
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when "00" =>
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-- first part of word
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susm_i.tdc_fifo_data(15 downto 12) <= (others => '0');
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susm_i.tdc_fifo_data(11 downto 8) <= tdccounter(3 downto 0); -- tdc number
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susm_i.tdc_fifo_data(7 downto 0) <= tdccounter(23 downto 16); -- tdc timestamp
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when "01" =>
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-- second part of word
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susm_i.tdc_fifo_data(15 downto 0) <= tdccounter(15 downto 0); -- tdc timestamp
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when "10" =>
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-- last part of word
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tdccounter <= tdccounter + '1';
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susm_i.tdc_fifo_data(15 downto 8) <= (others => '0'); -- tdc timestamp
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susm_i.tdc_fifo_data(7 downto 0) <= tdccounter(7 downto 0); -- tdc width
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tdcwordcnt <= (others => '0');
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when others =>
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tdcwordcnt <= (others => '0');
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end case;
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end if;
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end if;
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end if;
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end process;
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-- susm_i.hydro_fifo_empty <= '0';
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-- susm_i.hydro_fifo_full <= '1';
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susm_i.tdc_fifo_empty <= '0';
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susm_i.tdc_fifo_full <= '1';
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end architecture rtl ; -- of dummy_susm
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--------------------------------------------------------------------------------
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-- Object : Entity work.tri_state
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-- Last modified : Fri Jun 28 14:46:56 2013.
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--------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.std_logic_unsigned.all;
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entity tri_state is
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port(
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i : in std_logic;
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o : out std_logic;
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oen : in std_logic);
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end entity tri_state;
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--------------------------------------------------------------------------------
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-- Object : Architecture work.tri_state.structure
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-- Last modified : Fri Jun 28 14:46:56 2013.
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--------------------------------------------------------------------------------
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architecture structure of tri_state is
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begin
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o <= i when (oen = '0') else 'Z';
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end architecture structure ; -- of tri_state
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--------------------------------------------------------------------------------
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-- Object : Entity work.DummySlave
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-- Last modified : Tue Jan 15 14:25:05 2013.
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--------------------------------------------------------------------------------
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library ieee, work;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.std_logic_unsigned.all;
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use work.wishbone_pkg.all;
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entity DummySlave is
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port(
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slave_i : out t_wishbone_slave_in;
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slave_o : out t_wishbone_slave_out);
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end entity DummySlave;
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--------------------------------------------------------------------------------
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-- Object : Architecture work.DummySlave.a0
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-- Last modified : Tue Jan 15 14:25:05 2013.
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--------------------------------------------------------------------------------
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architecture a0 of DummySlave is
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begin
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-- Slave input wishbone signals
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slave_i.cyc <= '0';
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slave_i.stb <= '0';
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slave_i.adr <= (Others => '0');
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slave_i.sel <= "0000";
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slave_i.we <= '0';
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slave_i.dat <= (Others => '0');
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-- Slave output wishbone signals
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slave_o.ack <= '0';
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slave_o.err <= '0';
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slave_o.rty <= '0';
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slave_o.stall <= '0';
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slave_o.int <= '0';
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slave_o.dat <= (Others => '0');
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end architecture a0 ; -- of DummySlave
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--------------------------------------------------------------------------------
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-- Object : Entity work.Dum_mnic
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-- Last modified : Tue Jan 15 14:28:09 2013.
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--------------------------------------------------------------------------------
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library ieee, work;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.std_logic_unsigned.all;
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use work.genram_pkg.all;
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use work.wishbone_pkg.all;
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entity Dum_mnic is
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generic(
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g_dpram_size : integer := 20480);
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port(
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dpram_wbb_i : out t_wishbone_slave_in;
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dpram_wbb_o : in t_wishbone_slave_out);
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end entity Dum_mnic;
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--------------------------------------------------------------------------------
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-- Object : Architecture work.Dum_mnic.a0
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-- Last modified : Tue Jan 15 14:28:09 2013.
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--------------------------------------------------------------------------------
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architecture a0 of Dum_mnic is
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constant c_mnic_memsize_log2 : integer := f_log2_size(g_dpram_size);
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begin
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dpram_wbb_i.cyc <= '1';
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dpram_wbb_i.stb <= '1';
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dpram_wbb_i.adr(c_mnic_memsize_log2-1 downto 0) <= "000000000000000";
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dpram_wbb_i.sel <= "1111";
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dpram_wbb_i.we <= '0';
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dpram_wbb_i.dat <= "00000000000000000000000000000000";
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-- mnic_mem_data_i <= dpram_wbb_o.dat;
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end architecture a0 ; -- of Dum_mnic
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--------------------------------------------------------------------------------
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-- Object : Entity work.lm32_2nd
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-- Last modified : Fri Sep 20 13:18:24 2013.
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--------------------------------------------------------------------------------
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library ieee, work;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.std_logic_unsigned.all;
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use work.wishbone_pkg.all;
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use work.endpoint_pkg.all;
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use work.wrcore_pkg.all;
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use work.lm32_2nd_pkg.all;
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use work.tdc_pkg.all;
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use work.aes_pkg.all;
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use work.susm_pkg.all;
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entity lm32_2nd is
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generic(
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g_dpram_size : natural := 20480;
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g_date_id : integer := 0;
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g_revision_id : integer := 0);
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port(
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GPIO_LED : inout std_logic_vector(5 downto 0);
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DIP_SWITCH : inout std_logic_vector(3 downto 0);
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GPIO_TEST : inout std_logic_vector(3 downto 0);
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-- GPIO_LED : out std_logic_vector(6 downto 0);
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RST_TEST : inout std_logic;
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RST_TEST_N : inout std_logic;
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RST_TEST_OUT : inout std_logic;
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aes_i : in t_aes_in;
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aes_o : out t_aes_out;
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susm_i : in t_susm_in;
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susm_o : out t_susm_out;
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clk_sys_i : in std_logic;
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irq_i : in std_logic_vector(31 downto 0);
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pad_cs_o : out std_logic;
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pad_miso_i : in std_logic;
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pad_mosi_o : out std_logic;
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pad_sclk_o : out std_logic;
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rst_n_i : in std_logic;
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sRx : in std_logic;
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sTx : out std_logic;
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sRx2 : in std_logic; -- for UART2
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sTx2 : out std_logic; -- for UART2
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scl1 : inout std_logic;
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scl2 : inout std_logic;
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sda1 : inout std_logic;
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sda2 : inout std_logic;
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tdc_i : in t_tdc_in;
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tdc_o : out t_tdc_out;
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phy_txclk : in std_logic;
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phy_rxclk : in std_logic;
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phy_rxd : in std_logic_vector(3 downto 0);
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phy_rxdv : in std_logic;
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phy_rxer : in std_logic;
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phy_col : in std_logic;
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phy_crs : in std_logic;
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phy_txd : out std_logic_vector(3 downto 0);
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phy_txen : out std_logic;
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phy_txer : out std_logic;
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phy_mdc : out std_logic;
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phy_mdio : inout std_logic;
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data_out_to_pins_p : out std_logic_vector(30 downto 0);
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data_out_to_pins_n : out std_logic_vector(30 downto 0);
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clk_serial_in : in std_logic;
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areset_parallel : in std_logic;
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locked_clks : in std_logic;
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VP_IN : IN std_logic;
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VN_IN : IN std_logic
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);
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end entity lm32_2nd;
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--------------------------------------------------------------------------------
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-- Object : Architecture work.lm32_2nd.a0
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-- Last modified : Fri Sep 20 13:18:24 2013.
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--------------------------------------------------------------------------------
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architecture a0 of lm32_2nd is
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-----------------------------------------------------------------------------
|
|
--WB Secondary Crossbar
|
|
-----------------------------------------------------------------------------
|
|
constant c_secbar_layout : t_sdb_record_array(18 downto 0) :=
|
|
(0 => f_sdb_embed_device(c_wrc_periph1_sdb, x"00000000"), -- UART
|
|
1 => f_sdb_embed_device(c_tdc_sdb, x"00000100"), -- TDCs
|
|
2 => f_sdb_embed_device(c_aes_sdb, x"00000200"), -- AES
|
|
3 => f_sdb_embed_device(c_wrc_periph4_sdb, x"00000300"), -- GPIO
|
|
4 => f_sdb_embed_device(c_wrc_periph5_sdb, x"00000400"), -- SPI
|
|
5 => f_sdb_embed_device(c_wrc_periph6_sdb, x"00000500"), -- I2C1
|
|
6 => f_sdb_embed_device(c_wrc_periph6_sdb, x"00000600"), -- I2C2
|
|
7 => f_sdb_embed_device(c_wrc_periph7_sdb, x"00000700"), -- Timer
|
|
8 => f_sdb_embed_device(c_wrc_periph8_sdb, x"00000800"), -- DATE_REVISION_ID
|
|
9 => f_sdb_embed_device(c_susm_sdb, x"00000900"), -- SUSM
|
|
10 => f_sdb_embed_device(c_wrc_periph1_sdb, x"00000A00"), -- UART2
|
|
11 => f_sdb_embed_device(c_wrc_periph3_sdb, x"00000B00"),
|
|
12 => f_sdb_embed_device(c_wrc_periph3_sdb, x"00000C00"),
|
|
13 => f_sdb_embed_device(c_wrc_periph3_sdb, x"00000D00"),
|
|
14 => f_sdb_embed_device(c_wrc_periph3_sdb, x"00000E00"),
|
|
15 => f_sdb_embed_device(c_wrc_periph3_sdb, x"00000F00"),
|
|
16 => f_sdb_embed_device(c_ethmac_sdb, x"0000A000"), --Ethernet MAC 10/100
|
|
17 => f_sdb_embed_device(c_xadc_sdb, x"0000B000"), --XADC
|
|
18 => f_sdb_embed_device(c_pso_sdb, x"0000C000") -- PSO
|
|
);
|
|
|
|
constant c_secbar_sdb_address : t_wishbone_address := x"00001000";
|
|
constant c_secbar_bridge_sdb : t_sdb_bridge :=
|
|
f_xwb_bridge_layout_sdb(true, c_secbar_layout, c_secbar_sdb_address);
|
|
|
|
-----------------------------------------------------------------------------
|
|
--WB intercon
|
|
-----------------------------------------------------------------------------
|
|
constant c_layout : t_sdb_record_array(1 downto 0) :=
|
|
(0 => f_sdb_embed_device(f_xwb_dpram(g_dpram_size), x"00000000"),
|
|
1 => f_sdb_embed_bridge(c_secbar_bridge_sdb, x"00040000"));
|
|
constant c_sdb_address : t_wishbone_address := x"00050000";
|
|
|
|
|
|
signal cbar_slave_i : t_wishbone_slave_in_array(1 downto 0);
|
|
signal cbar_slave_o : t_wishbone_slave_out_array(1 downto 0);
|
|
signal cbar_master_i : t_wishbone_master_in_array(1 downto 0);
|
|
signal cbar_master_o : t_wishbone_master_out_array(1 downto 0);
|
|
signal slave2_o : t_wishbone_slave_out;
|
|
signal dpram_wbb_i : t_wishbone_slave_in;
|
|
signal secbar_master_i : t_wishbone_master_in_array(18 downto 0);
|
|
signal secbar_master_o : t_wishbone_master_out_array(18 downto 0);
|
|
signal xwb_sdb_crossbar_slave_i : t_wishbone_slave_in_array(0 downto 0);
|
|
signal xwb_sdb_crossbar_slave_o : t_wishbone_slave_out_array(0 downto 0);
|
|
signal scl_pad_o : std_logic;
|
|
signal scl_padoen_o : std_logic;
|
|
signal sda_pad_o : std_logic;
|
|
signal sda_padoen_o : std_logic;
|
|
signal Net_21 : std_logic;
|
|
signal Net_22 : std_logic;
|
|
signal Net_24 : std_logic;
|
|
signal Net_25 : std_logic;
|
|
signal u18_pad_cs_o : std_logic_vector(7 downto 0);
|
|
|
|
component Dum_mnic
|
|
generic(
|
|
g_dpram_size : integer := 20480);
|
|
port(
|
|
dpram_wbb_i : out t_wishbone_slave_in;
|
|
dpram_wbb_o : in t_wishbone_slave_out);
|
|
end component Dum_mnic;
|
|
|
|
component DummySlave
|
|
port(
|
|
slave_i : out t_wishbone_slave_in;
|
|
slave_o : out t_wishbone_slave_out);
|
|
end component DummySlave;
|
|
|
|
component xwb_lm32
|
|
generic(
|
|
g_profile : string := "medium_icache_debug");
|
|
port(
|
|
clk_sys_i : in std_logic;
|
|
dwb_i : in t_wishbone_master_in;
|
|
dwb_o : out t_wishbone_master_out;
|
|
irq_i : in std_logic_vector(31 downto 0);
|
|
iwb_i : in t_wishbone_master_in;
|
|
iwb_o : out t_wishbone_master_out;
|
|
rst_n_i : in std_logic);
|
|
end component xwb_lm32;
|
|
|
|
component xwb_dpram
|
|
generic(
|
|
g_init_file : string := "";
|
|
g_must_have_init_file : boolean := true;
|
|
g_slave2_interface_mode : t_wishbone_interface_mode := PIPELINED;
|
|
g_slave2_granularity : t_wishbone_address_granularity := WORD;
|
|
g_size : natural := 16384;
|
|
g_slave1_interface_mode : t_wishbone_interface_mode := PIPELINED;
|
|
g_slave1_granularity : t_wishbone_address_granularity := WORD);
|
|
port(
|
|
clk_sys_i : in std_logic;
|
|
rst_n_i : in std_logic;
|
|
slave1_i : in t_wishbone_slave_in;
|
|
slave1_o : out t_wishbone_slave_out;
|
|
slave2_i : in t_wishbone_slave_in;
|
|
slave2_o : out t_wishbone_slave_out);
|
|
end component xwb_dpram;
|
|
|
|
component xwb_sdb_crossbar
|
|
generic(
|
|
g_num_masters : integer := 3;
|
|
g_registered : boolean := true;
|
|
g_layout : t_sdb_record_array;
|
|
g_num_slaves : integer := 2;
|
|
g_wraparound : boolean := true;
|
|
g_sdb_addr : t_wishbone_address := x"00000000");
|
|
port(
|
|
clk_sys_i : in std_logic;
|
|
master_i : in t_wishbone_master_in_array(g_num_slaves-1 downto 0);
|
|
master_o : out t_wishbone_master_out_array(g_num_slaves-1 downto 0);
|
|
rst_n_i : in std_logic;
|
|
slave_i : in t_wishbone_slave_in_array(g_num_masters-1 downto 0);
|
|
slave_o : out t_wishbone_slave_out_array(g_num_masters-1 downto 0));
|
|
end component xwb_sdb_crossbar;
|
|
|
|
component xwb_simple_uart
|
|
generic(
|
|
g_with_virtual_uart : boolean := False;
|
|
g_with_physical_uart : boolean := True;
|
|
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
|
|
g_address_granularity : t_wishbone_address_granularity := WORD);
|
|
port(
|
|
clk_sys_i : in std_logic;
|
|
rst_n_i : in std_logic;
|
|
slave_i : in t_wishbone_slave_in;
|
|
slave_o : out t_wishbone_slave_out;
|
|
uart_rxd_i : in std_logic;
|
|
uart_txd_o : out std_logic);
|
|
end component xwb_simple_uart;
|
|
|
|
component xwb_tics
|
|
generic(
|
|
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
|
|
g_address_granularity : t_wishbone_address_granularity := WORD;
|
|
g_period : integer := 100);
|
|
port(
|
|
clk_sys_i : in std_logic;
|
|
desc_o : out t_wishbone_device_descriptor;
|
|
rst_n_i : in std_logic;
|
|
slave_i : in t_wishbone_slave_in;
|
|
slave_o : out t_wishbone_slave_out);
|
|
end component xwb_tics;
|
|
|
|
component xwb_gpio_port
|
|
generic(
|
|
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
|
|
g_address_granularity : t_wishbone_address_granularity := WORD;
|
|
g_num_pins : natural range 1 to 256 := 32;
|
|
g_with_builtin_tristates : boolean := false);
|
|
port(
|
|
clk_sys_i : in std_logic;
|
|
desc_o : out t_wishbone_device_descriptor;
|
|
gpio_b : inout std_logic_vector(g_num_pins-1 downto 0);
|
|
gpio_in_i : in std_logic_vector(g_num_pins-1 downto 0);
|
|
gpio_oen_o : out std_logic_vector(g_num_pins-1 downto 0);
|
|
gpio_out_o : out std_logic_vector(g_num_pins-1 downto 0);
|
|
rst_n_i : in std_logic;
|
|
slave_i : in t_wishbone_slave_in;
|
|
slave_o : out t_wishbone_slave_out);
|
|
end component xwb_gpio_port;
|
|
|
|
component xwb_i2c_master
|
|
generic(
|
|
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
|
|
g_address_granularity : t_wishbone_address_granularity := WORD);
|
|
port(
|
|
clk_sys_i : in std_logic;
|
|
desc_o : out t_wishbone_device_descriptor;
|
|
rst_n_i : in std_logic;
|
|
scl_pad_i : in std_logic;
|
|
scl_pad_o : out std_logic;
|
|
scl_padoen_o : out std_logic;
|
|
sda_pad_i : in std_logic;
|
|
sda_pad_o : out std_logic;
|
|
sda_padoen_o : out std_logic;
|
|
slave_i : in t_wishbone_slave_in;
|
|
slave_o : out t_wishbone_slave_out);
|
|
end component xwb_i2c_master;
|
|
|
|
component tri_state
|
|
port(
|
|
i : in std_logic;
|
|
o : out std_logic;
|
|
oen : in std_logic);
|
|
end component tri_state;
|
|
|
|
component xwb_date_rev_id
|
|
generic(
|
|
g_date_id : integer := 0;
|
|
g_revision_id : integer := 0;
|
|
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
|
|
g_address_granularity : t_wishbone_address_granularity := WORD);
|
|
port(
|
|
clk_sys_i : in std_logic;
|
|
rst_n_i : in std_logic;
|
|
slave_i : in t_wishbone_slave_in;
|
|
slave_o : out t_wishbone_slave_out);
|
|
end component xwb_date_rev_id;
|
|
|
|
component xwb_spi
|
|
generic(
|
|
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
|
|
g_address_granularity : t_wishbone_address_granularity := WORD);
|
|
port(
|
|
clk_sys_i : in std_logic;
|
|
desc_o : out t_wishbone_device_descriptor;
|
|
pad_cs_o : out std_logic_vector(7 downto 0);
|
|
pad_miso_i : in std_logic;
|
|
pad_mosi_o : out std_logic;
|
|
pad_sclk_o : out std_logic;
|
|
rst_n_i : in std_logic;
|
|
slave_i : in t_wishbone_slave_in;
|
|
slave_o : out t_wishbone_slave_out);
|
|
end component xwb_spi;
|
|
|
|
component xwb_tdc
|
|
generic(
|
|
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
|
|
g_address_granularity : t_wishbone_address_granularity := WORD;
|
|
g_channels : integer := 31);
|
|
port(
|
|
clk_sys_i : in std_logic;
|
|
desc_o : out t_wishbone_device_descriptor;
|
|
rst_n_i : in std_logic;
|
|
slave_i : in t_wishbone_slave_in;
|
|
slave_o : out t_wishbone_slave_out;
|
|
tdc_i : in t_tdc_in;
|
|
tdc_o : out t_tdc_out);
|
|
end component xwb_tdc;
|
|
|
|
component xwb_aes
|
|
generic(
|
|
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
|
|
g_address_granularity : t_wishbone_address_granularity := WORD;
|
|
g_word_size : integer := 64);
|
|
port(
|
|
aes_i : in t_aes_in;
|
|
aes_o : out t_aes_out;
|
|
clk_sys_i : in std_logic;
|
|
desc_o : out t_wishbone_device_descriptor;
|
|
rst_n_i : in std_logic;
|
|
slave_i : in t_wishbone_slave_in;
|
|
slave_o : out t_wishbone_slave_out);
|
|
end component xwb_aes;
|
|
|
|
component xwb_susm
|
|
generic(
|
|
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
|
|
g_address_granularity : t_wishbone_address_granularity := WORD);
|
|
port(
|
|
susm_i : in t_susm_in;
|
|
susm_o : out t_susm_out;
|
|
clk_sys_i : in std_logic;
|
|
desc_o : out t_wishbone_device_descriptor;
|
|
rst_n_i : in std_logic;
|
|
slave_i : in t_wishbone_slave_in;
|
|
slave_o : out t_wishbone_slave_out);
|
|
end component xwb_susm;
|
|
|
|
component xwb_ethernet_mac
|
|
generic(
|
|
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
|
|
g_address_granularity : t_wishbone_address_granularity := WORD
|
|
);
|
|
port (
|
|
clk_sys_i : in std_logic;
|
|
rst_n_i : in std_logic;
|
|
slave_i : in t_wishbone_slave_in;
|
|
slave_o : out t_wishbone_slave_out;
|
|
master_i : in t_wishbone_master_in;
|
|
master_o : out t_wishbone_master_out;
|
|
mtx_clk_pad_i : IN std_logic;
|
|
mrx_clk_pad_i : IN std_logic;
|
|
mrxd_pad_i : IN std_logic_vector(3 downto 0);
|
|
mrxdv_pad_i : IN std_logic;
|
|
mrxerr_pad_i : IN std_logic;
|
|
mcoll_pad_i : IN std_logic;
|
|
mcrs_pad_i : IN std_logic;
|
|
mtxd_pad_o : OUT std_logic_vector(3 downto 0);
|
|
mtxen_pad_o : OUT std_logic;
|
|
mtxerr_pad_o : OUT std_logic;
|
|
mdc_pad_o : OUT std_logic;
|
|
md_pad_i : IN std_logic;
|
|
md_pad_o : OUT std_logic;
|
|
md_padoe_o : OUT std_logic
|
|
);
|
|
end component;
|
|
|
|
signal md_pad_o, md_padoe_o : std_logic;
|
|
|
|
--component myicon
|
|
-- PORT (
|
|
-- CONTROL0 : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0));
|
|
--
|
|
--end component;
|
|
--
|
|
--component myila
|
|
-- PORT (
|
|
-- CONTROL : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0);
|
|
-- CLK : IN STD_LOGIC;
|
|
-- TRIG0 : IN STD_LOGIC_VECTOR(127 DOWNTO 0));
|
|
--
|
|
--end component;
|
|
--
|
|
-- signal CONTROL0 : STD_LOGIC_VECTOR(35 DOWNTO 0);
|
|
-- signal TRIG0 : STD_LOGIC_VECTOR(127 DOWNTO 0);
|
|
--
|
|
-- signal phy_txd_i : std_logic_vector(3 downto 0);
|
|
|
|
component xwb_pso
|
|
Generic (
|
|
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
|
|
g_address_granularity : t_wishbone_address_granularity := WORD
|
|
);
|
|
port(
|
|
clk_sys_i : in std_logic;
|
|
rst_n_i : in std_logic;
|
|
|
|
-----WISHBONE SIGNALS
|
|
slave_i : in t_wishbone_slave_in;
|
|
slave_o : out t_wishbone_slave_out;
|
|
desc_o : out t_wishbone_device_descriptor;
|
|
--custom signals
|
|
data_out_to_pins_p : out std_logic_vector(30 downto 0);
|
|
data_out_to_pins_n : out std_logic_vector(30 downto 0);
|
|
clk_serial_in : in std_logic; -- Slow clock from PLL/MMCM
|
|
areset_parallel : in std_logic; -- Async Reset signal for IO circuit
|
|
locked_clks : in std_logic );
|
|
end component;
|
|
|
|
|
|
component xwb_xadc
|
|
Generic (
|
|
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
|
|
g_address_granularity : t_wishbone_address_granularity := WORD
|
|
);
|
|
port(
|
|
clk_sys_i : in std_logic;
|
|
rst_n_i : in std_logic;
|
|
|
|
-----WISHBONE SIGNALS
|
|
slave_i : in t_wishbone_slave_in;
|
|
slave_o : out t_wishbone_slave_out;
|
|
desc_o : out t_wishbone_device_descriptor;
|
|
--custom signals
|
|
VP_IN : IN std_logic;
|
|
VN_IN : IN std_logic
|
|
);
|
|
end component;
|
|
|
|
begin
|
|
--cbar_slave(2) ought to be
|
|
--connected to the PCI-express brigde
|
|
--WB_CON
|
|
--WB_SECONDARY_CON
|
|
--period 1 ms
|
|
--@ clk_sys_i = 125 Mhz => g_period = 125000
|
|
--@ clk_sys_i = 62.5 Mhz => g_period = 62500
|
|
pad_cs_o <= u18_pad_cs_o(0);
|
|
-- u6: Dum_mnic
|
|
-- generic map(
|
|
-- g_dpram_size => g_dpram_size)
|
|
-- port map(
|
|
-- dpram_wbb_i => dpram_wbb_i,
|
|
-- dpram_wbb_o => slave2_o);
|
|
|
|
-- u2: DummySlave
|
|
-- port map(
|
|
-- slave_i => cbar_slave_i(2),
|
|
-- slave_o => cbar_slave_o(2));
|
|
|
|
u0: xwb_lm32
|
|
generic map(
|
|
g_profile => "medium_icache_debug")
|
|
port map(
|
|
clk_sys_i => clk_sys_i,
|
|
dwb_i => cbar_slave_o(0),
|
|
dwb_o => cbar_slave_i(0),
|
|
irq_i => irq_i,
|
|
iwb_i => cbar_slave_o(1),
|
|
iwb_o => cbar_slave_i(1),
|
|
rst_n_i => rst_n_i);
|
|
|
|
u4: xwb_dpram
|
|
generic map(
|
|
g_init_file => "lm32_memory.ldr",
|
|
g_must_have_init_file => true,
|
|
g_slave2_interface_mode => CLASSIC,
|
|
g_slave2_granularity => BYTE,
|
|
g_size => g_dpram_size,
|
|
g_slave1_interface_mode => PIPELINED,
|
|
g_slave1_granularity => BYTE)
|
|
port map(
|
|
clk_sys_i => clk_sys_i,
|
|
rst_n_i => rst_n_i,
|
|
slave1_i => cbar_master_o(0),
|
|
slave1_o => cbar_master_i(0),
|
|
slave2_i => dpram_wbb_i,
|
|
slave2_o => slave2_o);
|
|
|
|
u1: xwb_sdb_crossbar
|
|
generic map(
|
|
g_num_masters => 2,
|
|
g_registered => true,
|
|
g_layout => c_layout,
|
|
g_num_slaves => 2,
|
|
g_wraparound => true,
|
|
g_sdb_addr => c_sdb_address)
|
|
port map(
|
|
clk_sys_i => clk_sys_i,
|
|
master_i => cbar_master_i,
|
|
master_o => cbar_master_o,
|
|
rst_n_i => rst_n_i,
|
|
slave_i => cbar_slave_i,
|
|
slave_o => cbar_slave_o);
|
|
|
|
u9: xwb_sdb_crossbar
|
|
generic map(
|
|
g_num_masters => 1,
|
|
g_registered => true,
|
|
g_layout => c_secbar_layout,
|
|
g_num_slaves => 19,
|
|
g_wraparound => true,
|
|
g_sdb_addr => c_secbar_sdb_address)
|
|
port map(
|
|
clk_sys_i => clk_sys_i,
|
|
master_i => secbar_master_i,
|
|
master_o => secbar_master_o,
|
|
rst_n_i => rst_n_i,
|
|
slave_i => xwb_sdb_crossbar_slave_i,
|
|
slave_o => xwb_sdb_crossbar_slave_o);
|
|
|
|
u12: xwb_simple_uart
|
|
generic map(
|
|
g_with_virtual_uart => False,
|
|
g_with_physical_uart => True,
|
|
g_interface_mode => PIPELINED,
|
|
g_address_granularity => BYTE)
|
|
port map(
|
|
clk_sys_i => clk_sys_i,
|
|
rst_n_i => rst_n_i,
|
|
slave_i => secbar_master_o(0),
|
|
slave_o => secbar_master_i(0),
|
|
uart_rxd_i => sRx,
|
|
uart_txd_o => sTx);
|
|
|
|
u20: xwb_simple_uart
|
|
generic map(
|
|
g_with_virtual_uart => False,
|
|
g_with_physical_uart => True,
|
|
g_interface_mode => PIPELINED,
|
|
g_address_granularity => BYTE)
|
|
port map(
|
|
clk_sys_i => clk_sys_i,
|
|
rst_n_i => rst_n_i,
|
|
slave_i => secbar_master_o(10),
|
|
slave_o => secbar_master_i(10),
|
|
uart_rxd_i => sRx2,
|
|
uart_txd_o => sTx2);
|
|
|
|
u3: xwb_tics
|
|
generic map(
|
|
g_interface_mode => PIPELINED,
|
|
g_address_granularity => BYTE,
|
|
g_period => 62500)
|
|
port map(
|
|
clk_sys_i => clk_sys_i,
|
|
desc_o => open,
|
|
rst_n_i => rst_n_i,
|
|
slave_i => secbar_master_o(7),
|
|
slave_o => secbar_master_i(7));
|
|
|
|
u5: xwb_gpio_port
|
|
generic map(
|
|
g_interface_mode => PIPELINED,
|
|
g_address_granularity => BYTE,
|
|
g_num_pins => 256, -- 6 led, 8 dip-switch, 16 gpio (header)
|
|
g_with_builtin_tristates => TRUE) -- tri-state enabled
|
|
port map(
|
|
clk_sys_i => clk_sys_i,
|
|
desc_o => open,
|
|
gpio_b(255) => RST_TEST_OUT,
|
|
gpio_b(254 downto 32) => open, -- gpio
|
|
gpio_b(31) => RST_TEST,
|
|
gpio_b(30) => RST_TEST_N,
|
|
gpio_b(29 downto 18) => open, -- gpio
|
|
gpio_b(17 downto 14) => GPIO_TEST(3 downto 0), -- gpio
|
|
gpio_b(13 downto 10) => open, -- dip switch
|
|
gpio_b(9 downto 6) => DIP_SWITCH(3 downto 0), -- dip switch
|
|
gpio_b(5 downto 0) => GPIO_LED(5 downto 0), -- led
|
|
gpio_in_i => (others => '0'),
|
|
gpio_oen_o => open,
|
|
gpio_out_o => open,
|
|
rst_n_i => rst_n_i,
|
|
slave_i => secbar_master_o(3),
|
|
slave_o => secbar_master_i(3));
|
|
-- u5: xwb_gpio_port
|
|
-- generic map(
|
|
-- g_interface_mode => PIPELINED,
|
|
-- g_address_granularity => BYTE,
|
|
-- g_num_pins => 7,
|
|
-- g_with_builtin_tristates => FALSE)
|
|
-- port map(
|
|
-- clk_sys_i => clk_sys_i,
|
|
-- desc_o => open,
|
|
-- gpio_b => open,
|
|
-- gpio_in_i => "0000000",
|
|
-- gpio_oen_o => open,
|
|
-- gpio_out_o => GPIO_LED,
|
|
-- rst_n_i => rst_n_i,
|
|
-- slave_i => secbar_master_o(3),
|
|
-- slave_o => secbar_master_i(3));
|
|
|
|
u7: xwb_i2c_master
|
|
generic map(
|
|
g_interface_mode => PIPELINED,
|
|
g_address_granularity => BYTE)
|
|
port map(
|
|
clk_sys_i => clk_sys_i,
|
|
desc_o => open,
|
|
rst_n_i => rst_n_i,
|
|
scl_pad_i => scl1,
|
|
scl_pad_o => scl_pad_o,
|
|
scl_padoen_o => scl_padoen_o,
|
|
sda_pad_i => sda1,
|
|
sda_pad_o => sda_pad_o,
|
|
sda_padoen_o => sda_padoen_o,
|
|
slave_i => secbar_master_o(5),
|
|
slave_o => secbar_master_i(5));
|
|
|
|
u8: tri_state
|
|
port map(
|
|
i => scl_pad_o,
|
|
o => scl1,
|
|
oen => scl_padoen_o);
|
|
|
|
u10: tri_state
|
|
port map(
|
|
i => sda_pad_o,
|
|
o => sda1,
|
|
oen => sda_padoen_o);
|
|
|
|
u14: xwb_i2c_master
|
|
generic map(
|
|
g_interface_mode => PIPELINED,
|
|
g_address_granularity => BYTE)
|
|
port map(
|
|
clk_sys_i => clk_sys_i,
|
|
desc_o => open,
|
|
rst_n_i => rst_n_i,
|
|
scl_pad_i => scl2,
|
|
scl_pad_o => Net_21,
|
|
scl_padoen_o => Net_22,
|
|
sda_pad_i => sda2,
|
|
sda_pad_o => Net_24,
|
|
sda_padoen_o => Net_25,
|
|
slave_i => secbar_master_o(6),
|
|
slave_o => secbar_master_i(6));
|
|
|
|
u16: tri_state
|
|
port map(
|
|
i => Net_21,
|
|
o => scl2,
|
|
oen => Net_22);
|
|
|
|
u17: tri_state
|
|
port map(
|
|
i => Net_24,
|
|
o => sda2,
|
|
oen => Net_25);
|
|
|
|
u15: xwb_date_rev_id
|
|
generic map(
|
|
g_date_id => g_date_id,
|
|
g_revision_id => g_revision_id,
|
|
g_interface_mode => CLASSIC,
|
|
g_address_granularity => WORD)
|
|
port map(
|
|
clk_sys_i => clk_sys_i,
|
|
rst_n_i => rst_n_i,
|
|
slave_i => secbar_master_o(8),
|
|
slave_o => secbar_master_i(8));
|
|
|
|
u18: xwb_spi
|
|
generic map(
|
|
g_interface_mode => PIPELINED,
|
|
g_address_granularity => BYTE)
|
|
port map(
|
|
clk_sys_i => clk_sys_i,
|
|
desc_o => open,
|
|
pad_cs_o => u18_pad_cs_o,
|
|
pad_miso_i => pad_miso_i,
|
|
pad_mosi_o => pad_mosi_o,
|
|
pad_sclk_o => pad_sclk_o,
|
|
rst_n_i => rst_n_i,
|
|
slave_i => secbar_master_o(4),
|
|
slave_o => secbar_master_i(4));
|
|
|
|
u11: xwb_tdc
|
|
generic map(
|
|
g_interface_mode => PIPELINED,
|
|
g_address_granularity => BYTE,
|
|
g_channels => c_tdc_channels)
|
|
port map(
|
|
clk_sys_i => clk_sys_i,
|
|
desc_o => open,
|
|
rst_n_i => rst_n_i,
|
|
slave_i => secbar_master_o(1),
|
|
slave_o => secbar_master_i(1),
|
|
tdc_i => tdc_i,
|
|
tdc_o => tdc_o);
|
|
|
|
u19: xwb_aes
|
|
generic map(
|
|
g_interface_mode => PIPELINED,
|
|
g_address_granularity => BYTE,
|
|
g_word_size => c_aes_word_size)
|
|
port map(
|
|
aes_i => aes_i,
|
|
aes_o => aes_o,
|
|
clk_sys_i => clk_sys_i,
|
|
desc_o => open,
|
|
rst_n_i => rst_n_i,
|
|
slave_i => secbar_master_o(2),
|
|
slave_o => secbar_master_i(2));
|
|
|
|
u13: xwb_susm
|
|
generic map(
|
|
g_interface_mode => PIPELINED,
|
|
g_address_granularity => BYTE)
|
|
port map(
|
|
susm_i => susm_i,
|
|
susm_o => susm_o,
|
|
clk_sys_i => clk_sys_i,
|
|
desc_o => open,
|
|
rst_n_i => rst_n_i,
|
|
slave_i => secbar_master_o(9),
|
|
slave_o => secbar_master_i(9));
|
|
|
|
|
|
|
|
u6: xwb_ethernet_mac
|
|
generic map(
|
|
g_interface_mode => PIPELINED,
|
|
g_address_granularity => BYTE
|
|
)
|
|
port map(
|
|
clk_sys_i => clk_sys_i,
|
|
rst_n_i => rst_n_i,
|
|
slave_i => secbar_master_o(16), --cbar_master_o(2), --secbar_master_o(9),
|
|
slave_o => secbar_master_i(16), --cbar_master_i(2), --secbar_master_i(9),
|
|
master_i => slave2_o,
|
|
master_o => dpram_wbb_i,
|
|
mtx_clk_pad_i => phy_txclk,
|
|
mrx_clk_pad_i => phy_rxclk,
|
|
mrxd_pad_i => phy_rxd,
|
|
mrxdv_pad_i => phy_rxdv,
|
|
mrxerr_pad_i => phy_rxer,
|
|
mcoll_pad_i => phy_col,
|
|
mcrs_pad_i => phy_crs,
|
|
mtxd_pad_o => phy_txd,
|
|
mtxen_pad_o => phy_txen,
|
|
mtxerr_pad_o => phy_txer,
|
|
mdc_pad_o => phy_mdc, --phy_mdc_i,
|
|
md_pad_i => phy_mdio,
|
|
md_pad_o => md_pad_o,
|
|
md_padoe_o => md_padoe_o
|
|
);
|
|
|
|
|
|
u26: tri_state
|
|
port map(
|
|
i => md_pad_o,
|
|
o => phy_mdio,
|
|
oen => not(md_padoe_o));
|
|
|
|
|
|
--u100 : myicon
|
|
-- port map (
|
|
-- CONTROL0 => CONTROL0);
|
|
--
|
|
-- u101 : myila
|
|
-- port map (
|
|
-- CONTROL => CONTROL0,
|
|
-- CLK => clk_sys_i,
|
|
-- TRIG0 => TRIG0);
|
|
--
|
|
-- phy_txd <= phy_txd_i;
|
|
--
|
|
-- TRIG0(0) <= phy_txclk;
|
|
-- TRIG0(4 downto 1) <= phy_txd_i;
|
|
-- TRIG0(5) <= secbar_master_o(16).cyc;
|
|
-- TRIG0(6) <= secbar_master_o(16).stb;
|
|
-- TRIG0(16 downto 7) <= secbar_master_o(16).adr(11 downto 2);
|
|
-- TRIG0(48 downto 17) <= secbar_master_o(16).dat;
|
|
-- TRIG0(49) <= secbar_master_i(16).ack;
|
|
-- TRIG0(50) <= dpram_wbb_i.cyc;
|
|
-- TRIG0(51) <= dpram_wbb_i.stb;
|
|
-- TRIG0(52) <= slave2_o.ack;
|
|
|
|
u21: DummySlave
|
|
port map(
|
|
slave_i => open,
|
|
slave_o => secbar_master_i(11));
|
|
|
|
u27: xwb_pso
|
|
generic map(
|
|
g_interface_mode => PIPELINED,
|
|
g_address_granularity => BYTE
|
|
)
|
|
port map(
|
|
clk_sys_i => clk_sys_i,
|
|
rst_n_i => rst_n_i,
|
|
slave_i => secbar_master_o(18),
|
|
slave_o => secbar_master_i(18),
|
|
desc_o => open,
|
|
data_out_to_pins_p => data_out_to_pins_p,
|
|
data_out_to_pins_n => data_out_to_pins_n,
|
|
clk_serial_in => clk_serial_in,
|
|
areset_parallel => areset_parallel,
|
|
locked_clks => locked_clks
|
|
);
|
|
|
|
|
|
u2: xwb_xadc
|
|
Generic map (
|
|
g_interface_mode => PIPELINED,
|
|
g_address_granularity => BYTE
|
|
)
|
|
port map(
|
|
clk_sys_i => clk_sys_i,
|
|
rst_n_i => rst_n_i,
|
|
slave_i => secbar_master_o(17),
|
|
slave_o => secbar_master_i(17),
|
|
desc_o => open,
|
|
--custom signals
|
|
VP_IN => VP_IN,
|
|
VN_IN => VN_IN
|
|
);
|
|
|
|
|
|
u22: DummySlave
|
|
port map(
|
|
slave_i => open,
|
|
slave_o => secbar_master_i(12));
|
|
|
|
|
|
u23: DummySlave
|
|
port map(
|
|
slave_i => open,
|
|
slave_o => secbar_master_i(13));
|
|
|
|
u24: DummySlave
|
|
port map(
|
|
slave_i => open,
|
|
slave_o => secbar_master_i(14));
|
|
|
|
u25: DummySlave
|
|
port map(
|
|
slave_i => open,
|
|
slave_o => secbar_master_i(15));
|
|
|
|
|
|
xwb_sdb_crossbar_slave_i(0) <= cbar_master_o(1);
|
|
cbar_master_i(1) <= xwb_sdb_crossbar_slave_o(0);
|
|
end architecture a0 ; -- of lm32_2nd
|
|
|
|
--------------------------------------------------------------------------------
|
|
-- Object : Entity work.Reg1NoRst
|
|
-- Last modified : Mon Jan 14 15:05:41 2013.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
|
|
library ieee;
|
|
use ieee.std_logic_1164.all;
|
|
use ieee.numeric_std.all;
|
|
use ieee.std_logic_unsigned.all;
|
|
|
|
entity Reg1NoRst is
|
|
port(
|
|
Clk : in std_logic;
|
|
D : in std_logic;
|
|
O : out std_logic := '0';
|
|
O_n : out std_logic);
|
|
end entity Reg1NoRst;
|
|
|
|
--------------------------------------------------------------------------------
|
|
-- Object : Architecture work.Reg1NoRst.rtl
|
|
-- Last modified : Mon Jan 14 15:05:41 2013.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
architecture rtl of Reg1NoRst is
|
|
|
|
begin
|
|
Process (Clk)
|
|
Begin
|
|
If Rising_Edge(Clk) Then
|
|
O <= D;
|
|
O_n <= Not D;
|
|
End If;
|
|
End Process;
|
|
end architecture rtl ; -- of Reg1NoRst
|
|
|
|
--------------------------------------------------------------------------------
|
|
-- Object : Entity work.MetaStabelizer
|
|
-- Last modified : Mon Jan 14 15:05:19 2013.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
|
|
library ieee;
|
|
use ieee.std_logic_1164.all;
|
|
use ieee.numeric_std.all;
|
|
use ieee.std_logic_unsigned.all;
|
|
|
|
entity MetaStabelizer is
|
|
port(
|
|
Clk : in std_logic;
|
|
D : in std_logic;
|
|
O : out std_logic;
|
|
O_n : out std_logic);
|
|
end entity MetaStabelizer;
|
|
|
|
--------------------------------------------------------------------------------
|
|
-- Object : Architecture work.MetaStabelizer.rtl
|
|
-- Last modified : Mon Jan 14 15:05:19 2013.
|
|
--------------------------------------------------------------------------------
|
|
|
|
architecture rtl of MetaStabelizer is
|
|
|
|
signal O_net : std_logic := '0';
|
|
|
|
component Reg1NoRst
|
|
port(
|
|
Clk : in std_logic;
|
|
D : in std_logic;
|
|
O : out std_logic := '0';
|
|
O_n : out std_logic);
|
|
end component Reg1NoRst;
|
|
|
|
begin
|
|
u0: Reg1NoRst
|
|
port map(
|
|
Clk => Clk,
|
|
D => D,
|
|
O => O_net,
|
|
O_n => open);
|
|
|
|
u1: Reg1NoRst
|
|
port map(
|
|
Clk => Clk,
|
|
D => O_net,
|
|
O => O,
|
|
O_n => O_n);
|
|
|
|
end architecture rtl ; -- of MetaStabelizer
|
|
|
|
--------------------------------------------------------------------------------
|
|
-- Object : Entity work.Counter
|
|
-- Last modified : Mon Nov 19 11:51:35 2012.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
|
|
library ieee;
|
|
use ieee.std_logic_1164.all;
|
|
use ieee.numeric_std.all;
|
|
use ieee.std_logic_unsigned.all;
|
|
|
|
entity Counter is
|
|
port(
|
|
Clk : in std_logic;
|
|
Q : out std_logic_vector(31 downto 0);
|
|
Rst : in std_logic);
|
|
end entity Counter;
|
|
|
|
--------------------------------------------------------------------------------
|
|
-- Object : Architecture work.Counter.rtl
|
|
-- Last modified : Mon Nov 19 11:51:35 2012.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
architecture rtl of Counter is
|
|
|
|
begin
|
|
Process (Clk, Rst)
|
|
Variable Count: Unsigned(31 downto 0) := (Others => '0');
|
|
Begin
|
|
If Rst = '1' Then
|
|
Count := (Others => '0');
|
|
ElsIf Rising_Edge(Clk) Then
|
|
Count := Count + 1;
|
|
End If;
|
|
Q <= Std_Logic_Vector (Count);
|
|
End Process;
|
|
end architecture rtl ; -- of Counter
|
|
|
|
--------------------------------------------------------------------------------
|
|
-- Object : Entity work.fpga
|
|
-- Last modified : Fri Jul 05 14:23:51 2013.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
|
|
library ieee, work;
|
|
use ieee.std_logic_1164.all;
|
|
use ieee.numeric_std.all;
|
|
use ieee.std_logic_unsigned.all;
|
|
use work.wishbone_pkg.all;
|
|
use work.endpoint_pkg.all;
|
|
use work.wrcore_pkg.all;
|
|
use work.aes_pkg.all;
|
|
use work.susm_pkg.all;
|
|
use work.tdc_pkg.all;
|
|
|
|
entity fpga is
|
|
generic(
|
|
g_date_id : integer := 0;
|
|
g_revision_id : integer := 0;
|
|
g_dpram_size : natural := 20480);
|
|
port(
|
|
Blink : out std_logic;
|
|
ClkI_n : in std_logic;
|
|
ClkI_p : in std_logic;
|
|
GPIO_TEST : inout std_logic_vector(3 downto 2);
|
|
-- GPIO_TEST : inout std_logic_vector(3 downto 0);
|
|
DIP_SWITCH : inout std_logic_vector(3 downto 0);
|
|
GPIO_LED : inout std_logic_vector(5 downto 0);
|
|
-- GPIO_LED : out std_logic_vector(6 downto 0);
|
|
RST_I : in std_logic;
|
|
RST_TEST : inout std_logic;
|
|
RST_TEST_N : inout std_logic;
|
|
RST_TEST_OUT : inout std_logic;
|
|
AES_AUDIO_IN : in std_logic;
|
|
AES_CLK_OUT : out std_logic;
|
|
Spy2 : out std_logic;
|
|
Spy3 : out std_logic;
|
|
irq_0 : in std_logic;
|
|
irq_1 : in std_logic;
|
|
pad_cs_o : out std_logic;
|
|
pad_miso_i : in std_logic;
|
|
pad_mosi_o : out std_logic;
|
|
pad_sclk_o : out std_logic;
|
|
sRx : in std_logic;
|
|
sTx : out std_logic;
|
|
--sRx2 : in std_logic; -- for UART2
|
|
sTx2 : out std_logic; -- for UART2
|
|
scl1 : inout std_logic;
|
|
scl2 : inout std_logic;
|
|
sda1 : inout std_logic;
|
|
sda2 : inout std_logic;
|
|
|
|
-- -- EXPANSION ETHERNET
|
|
-- FMC_LA00_CC_P : in std_logic;
|
|
-- FMC_LA01_CC_P : in std_logic;
|
|
-- FMC_LA04_N : in std_logic;
|
|
-- FMC_LA04_P : in std_logic;
|
|
-- FMC_LA02_N : in std_logic;
|
|
-- FMC_LA02_P : in std_logic;
|
|
-- FMC_LA15_P : in std_logic;
|
|
-- FMC_LA15_N : in std_logic;
|
|
-- FMC_LA14_N : in std_logic;
|
|
-- FMC_LA14_P : in std_logic;
|
|
-- FMC_LA08_P : out std_logic;
|
|
-- FMC_LA12_N : out std_logic;
|
|
-- FMC_LA12_P : out std_logic;
|
|
-- FMC_LA09_N : out std_logic;
|
|
-- FMC_LA13_P : out std_logic;
|
|
-- FMC_LA10_N : out std_logic;
|
|
-- FMC_LA05_N : out std_logic;
|
|
-- FMC_LA06_N : inout std_logic;
|
|
-- FMC_LA09_P : out std_logic);
|
|
|
|
-- kc705 Ethernet
|
|
phy_txclk : in std_logic;
|
|
phy_rxclk : in std_logic;
|
|
phy_rxd : in std_logic_vector(3 downto 0);
|
|
phy_rxdv : in std_logic;
|
|
phy_rxer : in std_logic;
|
|
phy_col : in std_logic;
|
|
phy_crs : in std_logic;
|
|
phy_txd : out std_logic_vector(3 downto 0);
|
|
phy_txen : out std_logic;
|
|
phy_txer : out std_logic;
|
|
phy_mdc : out std_logic;
|
|
phy_mdio : inout std_logic;
|
|
phy_reset : out std_logic;
|
|
|
|
-- Pseudo Octopus TDC patterns
|
|
data_out_to_pins_p : out std_logic_vector(30 downto 0);
|
|
data_out_to_pins_n : out std_logic_vector(30 downto 0);
|
|
data_in_mon_p : in std_logic;
|
|
data_in_mon_n : in std_logic;
|
|
VP_IN : IN std_logic;
|
|
VN_IN : IN std_logic
|
|
);
|
|
end entity fpga;
|
|
|
|
--------------------------------------------------------------------------------
|
|
-- Object : Architecture work.fpga.a0
|
|
-- Last modified : Fri Jul 05 14:23:51 2013.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
--library UNISIM;
|
|
--use UNISIM.IBUFDS_GTE2;
|
|
|
|
architecture a0 of fpga is
|
|
|
|
signal Net_0 : std_logic_vector(31 downto 0);
|
|
signal u5_O : std_logic;
|
|
signal O_n : std_logic;
|
|
signal u7_O : std_logic;
|
|
signal Spy3_net : std_logic;
|
|
signal clk_62_5_o : std_logic;
|
|
signal clk_125_o : std_logic;
|
|
signal clk_500_o : std_logic;
|
|
signal clk_200_o : std_logic;
|
|
signal aes_i : t_aes_in;
|
|
signal aes_o : t_aes_out;
|
|
signal susm_i : t_susm_in;
|
|
signal susm_o : t_susm_out;
|
|
signal tdc_i : t_tdc_in;
|
|
signal irq_i : std_logic_vector(31 downto 0);
|
|
signal sRx2 : std_logic;
|
|
|
|
component Counter
|
|
port(
|
|
Clk : in std_logic;
|
|
Q : out std_logic_vector(31 downto 0);
|
|
Rst : in std_logic);
|
|
end component Counter;
|
|
|
|
component MetaStabelizer
|
|
port(
|
|
Clk : in std_logic;
|
|
D : in std_logic;
|
|
O : out std_logic;
|
|
O_n : out std_logic);
|
|
end component MetaStabelizer;
|
|
|
|
component IBUFDS_GTE2
|
|
port(
|
|
CEB : in std_logic;
|
|
I : in std_logic;
|
|
IB : in std_logic;
|
|
O : out std_logic;
|
|
ODIV2 : out std_logic);
|
|
end component IBUFDS_GTE2;
|
|
|
|
component lm32_2nd
|
|
generic(
|
|
g_dpram_size : natural := 20480;
|
|
g_date_id : integer := 0;
|
|
g_revision_id : integer := 0);
|
|
port(
|
|
GPIO_LED : inout std_logic_vector(5 downto 0);
|
|
DIP_SWITCH : inout std_logic_vector(3 downto 0);
|
|
GPIO_TEST : inout std_logic_vector(3 downto 0);
|
|
-- GPIO_LED : out std_logic_vector(6 downto 0);
|
|
RST_TEST : in std_logic;
|
|
RST_TEST_N : in std_logic;
|
|
RST_TEST_OUT : inout std_logic;
|
|
aes_i : in t_aes_in;
|
|
aes_o : out t_aes_out;
|
|
susm_i : in t_susm_in;
|
|
susm_o : out t_susm_out;
|
|
clk_sys_i : in std_logic;
|
|
irq_i : in std_logic_vector(31 downto 0);
|
|
pad_cs_o : out std_logic;
|
|
pad_miso_i : in std_logic;
|
|
pad_mosi_o : out std_logic;
|
|
pad_sclk_o : out std_logic;
|
|
rst_n_i : in std_logic;
|
|
sRx : in std_logic;
|
|
sTx : out std_logic;
|
|
sRx2 : in std_logic; -- for UART2
|
|
sTx2 : out std_logic; -- for UART2
|
|
scl1 : inout std_logic;
|
|
scl2 : inout std_logic;
|
|
sda1 : inout std_logic;
|
|
sda2 : inout std_logic;
|
|
tdc_i : in t_tdc_in;
|
|
tdc_o : out t_tdc_out;
|
|
phy_txclk : in std_logic;
|
|
phy_rxclk : in std_logic;
|
|
phy_rxd : in std_logic_vector(3 downto 0);
|
|
phy_rxdv : in std_logic;
|
|
phy_rxer : in std_logic;
|
|
phy_col : in std_logic;
|
|
phy_crs : in std_logic;
|
|
phy_txd : out std_logic_vector(3 downto 0);
|
|
phy_txen : out std_logic;
|
|
phy_txer : out std_logic;
|
|
phy_mdc : out std_logic;
|
|
phy_mdio : inout std_logic;
|
|
data_out_to_pins_p : out std_logic_vector(30 downto 0);
|
|
data_out_to_pins_n : out std_logic_vector(30 downto 0);
|
|
clk_serial_in : in std_logic;
|
|
areset_parallel : in std_logic;
|
|
locked_clks : in std_logic;
|
|
VP_IN : IN std_logic;
|
|
VN_IN : IN std_logic );
|
|
end component lm32_2nd;
|
|
|
|
component cmp_sys_clk_pll
|
|
port(
|
|
clk_125_o : out std_logic;
|
|
clk_62_5_o : out std_logic;
|
|
clk_500_o : out std_logic;
|
|
clk_200_o : out std_logic;
|
|
clk_i : in std_logic;
|
|
locked_o : out std_logic;
|
|
rst_i : in std_logic);
|
|
end component cmp_sys_clk_pll;
|
|
|
|
component dummy_aes
|
|
port(
|
|
aes_i : out t_aes_in);
|
|
end component dummy_aes;
|
|
|
|
component dummy_susm
|
|
port(
|
|
clk_i : in std_logic;
|
|
rst_i : in std_logic;
|
|
aes_fifo_rd : out std_logic;
|
|
aes_fifo_dout : in std_logic_vector(63 downto 0); -- data from decoded audio fifo
|
|
aes_fifo_full : in std_logic; -- decoded audio fifo full
|
|
aes_fifo_empty : in std_logic; -- decoded audio fifo empty
|
|
susm_i : out t_susm_in;
|
|
susm_o : in t_susm_out
|
|
);
|
|
end component dummy_susm;
|
|
|
|
component dummy_tdc
|
|
port(
|
|
tdc_i : out t_tdc_in);
|
|
end component dummy_tdc;
|
|
|
|
component low
|
|
generic(
|
|
n : integer := 8);
|
|
port(
|
|
o : out std_logic_vector(n-1 downto 0));
|
|
end component low;
|
|
|
|
signal locked_i : std_logic;
|
|
component monitor_serdes_custom
|
|
generic
|
|
(-- width of the data for the system
|
|
sys_w : integer := 1;
|
|
-- width of the data for the device
|
|
dev_w : integer := 8);
|
|
port
|
|
(
|
|
-- From the system into the device
|
|
DATA_IN_FROM_PINS_P : in std_logic_vector(sys_w-1 downto 0);
|
|
DATA_IN_FROM_PINS_N : in std_logic_vector(sys_w-1 downto 0);
|
|
DATA_IN_TO_DEVICE : out std_logic_vector(dev_w-1 downto 0);
|
|
|
|
BITSLIP : in std_logic; -- Bitslip module is enabled in NETWORKING mode
|
|
-- User should tie it to '0' if not needed
|
|
|
|
-- Clock and reset signals
|
|
CLK_IN : in std_logic; -- Fast clock from PLL/MMCM
|
|
CLK_DIV_IN : in std_logic; -- Slow clock from PLL/MMCM
|
|
IO_RESET : in std_logic;
|
|
REF_CLK : in std_logic); -- Reset signal for IO circuit
|
|
end component;
|
|
|
|
signal dataparmon : std_logic_vector(7 downto 0);
|
|
|
|
--component mon_icon
|
|
-- PORT (
|
|
-- CONTROL0 : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0));
|
|
--
|
|
--end component;
|
|
--
|
|
--
|
|
--signal CONTROL0 : STD_LOGIC_VECTOR(35 DOWNTO 0);
|
|
--
|
|
--component mon_ila
|
|
-- PORT (
|
|
-- CONTROL : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0);
|
|
-- CLK : IN STD_LOGIC;
|
|
-- TRIG0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0));
|
|
--
|
|
--end component;
|
|
|
|
|
|
|
|
begin
|
|
--This Metastabelizer also synchronizes RST_I
|
|
--to the CLK_I clock domain. Such a synchronous
|
|
--reset may be necessary to avoid asynchronous
|
|
--signal changes on the wb_memory that could
|
|
--trigger false write actions...
|
|
--SGMIICLK_Q0_P (pin G8)
|
|
--SGMIICLK_Q0_N (pin G7)
|
|
--connect to 125 MHz Xtal on KC705
|
|
sRx2 <= '1';
|
|
Blink <= Net_0(24);
|
|
Spy2 <= Net_0(24);
|
|
sTx <= Spy3_net;
|
|
Spy3 <= Spy3_net;
|
|
u3: Counter
|
|
port map(
|
|
Clk => clk_62_5_o,
|
|
Q => Net_0,
|
|
Rst => u7_O);
|
|
|
|
u7: MetaStabelizer
|
|
port map(
|
|
Clk => clk_62_5_o,
|
|
D => RST_I,
|
|
O => u7_O,
|
|
O_n => O_n);
|
|
|
|
u5: IBUFDS_GTE2
|
|
port map(
|
|
CEB => '0',
|
|
I => ClkI_p,
|
|
IB => ClkI_n,
|
|
O => u5_O,
|
|
ODIV2 => open);
|
|
|
|
u0: lm32_2nd
|
|
generic map(
|
|
g_dpram_size => g_dpram_size,
|
|
g_date_id => g_date_id,
|
|
g_revision_id => g_revision_id)
|
|
port map(
|
|
GPIO_LED => GPIO_LED,
|
|
DIP_SWITCH => DIP_SWITCH,
|
|
GPIO_TEST(3 downto 2) => GPIO_TEST(3 downto 2),
|
|
GPIO_TEST (1 downto 0) => open,
|
|
-- GPIO_TEST => GPIO_TEST,
|
|
-- GPIO_LED => GPIO_LED,
|
|
RST_TEST => RST_TEST,
|
|
RST_TEST_N => RST_TEST_N,
|
|
RST_TEST_OUT => RST_TEST_OUT,
|
|
aes_i => aes_i,
|
|
aes_o => aes_o,
|
|
susm_i => susm_i,
|
|
susm_o => susm_o,
|
|
clk_sys_i => clk_62_5_o,
|
|
irq_i => irq_i,
|
|
pad_cs_o => pad_cs_o,
|
|
pad_miso_i => pad_miso_i,
|
|
pad_mosi_o => pad_mosi_o,
|
|
pad_sclk_o => pad_sclk_o,
|
|
rst_n_i => O_n,
|
|
sRx => sRx,
|
|
sTx => Spy3_net,
|
|
sRx2 => sRx2, -- for UART2
|
|
sTx2 => sTx2, -- for UART2
|
|
scl1 => scl1,
|
|
scl2 => scl2,
|
|
sda1 => sda1,
|
|
sda2 => sda2,
|
|
tdc_i => tdc_i,
|
|
tdc_o => open,
|
|
|
|
-- EXPANSION ETHERNET
|
|
-- phy_txclk => FMC_LA00_CC_P,
|
|
-- phy_rxclk => FMC_LA01_CC_P,
|
|
-- phy_rxd(3) => FMC_LA04_N,
|
|
-- phy_rxd(2) => FMC_LA04_P,
|
|
-- phy_rxd(1) => FMC_LA02_N,
|
|
-- phy_rxd(0) => FMC_LA02_P,
|
|
-- phy_rxdv => FMC_LA15_P,
|
|
-- phy_rxer => FMC_LA15_N,
|
|
-- phy_col => FMC_LA14_N,
|
|
-- phy_crs => FMC_LA14_P,
|
|
-- phy_txd(3) => FMC_LA08_P,
|
|
-- phy_txd(2) => FMC_LA12_N,
|
|
-- phy_txd(1) => FMC_LA12_P,
|
|
-- phy_txd(0) => FMC_LA09_N,
|
|
-- phy_txen => FMC_LA13_P,
|
|
-- phy_txer => FMC_LA10_N,
|
|
-- phy_mdc => FMC_LA05_N,
|
|
-- phy_mdio => FMC_LA06_N);
|
|
-- FMC_LA09_P <= O_n;
|
|
|
|
--KC705 Ethernet
|
|
phy_txclk => phy_txclk,
|
|
phy_rxclk => phy_rxclk,
|
|
phy_rxd => phy_rxd,
|
|
phy_rxdv => phy_rxdv,
|
|
phy_rxer => phy_rxer,
|
|
phy_col => phy_col,
|
|
phy_crs => phy_crs,
|
|
phy_txd => phy_txd,
|
|
phy_txen => phy_txen,
|
|
phy_txer => phy_txer,
|
|
phy_mdc => phy_mdc,
|
|
phy_mdio => phy_mdio,
|
|
|
|
-- pseudo octopus tdc patterns
|
|
data_out_to_pins_p => data_out_to_pins_p,
|
|
data_out_to_pins_n => data_out_to_pins_n,
|
|
clk_serial_in => clk_500_o,
|
|
areset_parallel => u7_O ,
|
|
locked_clks => locked_i ,
|
|
VP_IN => VP_IN,
|
|
VN_IN => VN_IN );
|
|
|
|
|
|
|
|
|
|
|
|
phy_reset <= O_n;
|
|
|
|
u1: cmp_sys_clk_pll
|
|
port map(
|
|
clk_125_o => clk_125_o,
|
|
clk_62_5_o => clk_62_5_o,
|
|
clk_500_o => clk_500_o,
|
|
clk_200_o => clk_200_o,
|
|
clk_i => u5_O,
|
|
locked_o => locked_i,
|
|
rst_i => '0');
|
|
|
|
-- aes module connection
|
|
AES_CLK_OUT <= aes_o.audio_clk;
|
|
aes_i.audio_in <= AES_AUDIO_IN;
|
|
aes_i.clk125M <= clk_125_o;
|
|
aes_i.timeslice_start <= '0';
|
|
-- -- periodic restart of timeslice
|
|
-- tslice_proc : process (clk_125_o)
|
|
-- variable myt : integer;
|
|
-- begin
|
|
-- if clk_125_o = '1' and clk_125_o'event then
|
|
-- aes_i.timeslice_start <= '0';
|
|
-- if u7_O = '1' then -- reset
|
|
-- myt := 0;
|
|
-- else
|
|
-- myt := myt + 1;
|
|
-- if myt = 1000000 then
|
|
-- myt := 0;
|
|
-- aes_i.timeslice_start <= '1';
|
|
-- end if;
|
|
-- end if;
|
|
-- end if;
|
|
-- end process;
|
|
-- u2: dummy_aes
|
|
-- port map(
|
|
-- aes_i => aes_i);
|
|
|
|
u10: dummy_susm
|
|
port map(
|
|
clk_i => clk_62_5_o,
|
|
rst_i => u7_O, -- un reset positive (magari, forse)
|
|
aes_fifo_rd => aes_i.fifo_rd,
|
|
aes_fifo_dout => aes_o.fifo_dout,
|
|
aes_fifo_full => aes_o.fifo_full,
|
|
aes_fifo_empty => aes_o.fifo_empty,
|
|
susm_i => susm_i,
|
|
susm_o => susm_o);
|
|
|
|
u4: dummy_tdc
|
|
port map(
|
|
tdc_i => tdc_i);
|
|
|
|
u6: MetaStabelizer
|
|
port map(
|
|
Clk => clk_62_5_o,
|
|
D => irq_1,
|
|
O => irq_i(1),
|
|
O_n => open);
|
|
|
|
u8: MetaStabelizer
|
|
port map(
|
|
Clk => clk_62_5_o,
|
|
D => irq_0,
|
|
O => irq_i(0),
|
|
O_n => open);
|
|
|
|
u9: low
|
|
generic map(
|
|
n => 30)
|
|
port map(
|
|
o => irq_i(31 downto 2));
|
|
|
|
inst_monsingletdc : monitor_serdes_custom
|
|
port map
|
|
(
|
|
-- From the system into the device
|
|
DATA_IN_FROM_PINS_P(0) => data_in_mon_p, --Input pins
|
|
DATA_IN_FROM_PINS_N(0) => data_in_mon_n, --Input pins
|
|
DATA_IN_TO_DEVICE => dataparmon, --Output pins
|
|
|
|
BITSLIP => '0', --Input pin
|
|
|
|
|
|
-- Clock and reset signals
|
|
CLK_IN => clk_500_o, -- Fast clock input from PLL/MMCM
|
|
CLK_DIV_IN => clk_62_5_o, -- Slow clock input from PLL/MMCM
|
|
IO_RESET => u7_O,
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REF_CLK => clk_200_o); --system reset
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-- myicon : mon_icon
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-- port map (
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-- CONTROL0 => CONTROL0);
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--
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-- myila : mon_ila
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-- port map (
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-- CONTROL => CONTROL0,
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-- CLK => clk_62_5_o,
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-- TRIG0 => dataparmon);
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end architecture a0 ; -- of fpga
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