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1600 lines
46 KiB
VHDL
1600 lines
46 KiB
VHDL
--------------------------------------------------------------------------------
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--
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-- This VHDL file was generated by EASE/HDL 7.4 Revision 9 from HDL Works B.V.
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--
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-- Ease library : work
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-- HDL library : work
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-- Host name : SERING
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-- User name : peterj
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-- Time stamp : Fri Sep 20 13:26:13 2013
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--
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-- Designed by :
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-- Company : HDL Works
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-- Project info :
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--
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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-- Object : Entity work.low
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-- Last modified : Fri Jul 05 14:23:51 2013.
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--------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.std_logic_unsigned.all;
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entity low is
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generic(
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n : integer := 8);
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port(
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o : out std_logic_vector(n-1 downto 0));
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end entity low;
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--------------------------------------------------------------------------------
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-- Object : Architecture work.low.structure
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-- Last modified : Fri Jul 05 14:23:51 2013.
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--------------------------------------------------------------------------------
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architecture structure of low is
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begin
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o <= (others => '0');
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end architecture structure ; -- of low
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--------------------------------------------------------------------------------
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-- Object : Entity work.dummy_tdc
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-- Last modified : Thu Jul 25 10:01:05 2013.
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--------------------------------------------------------------------------------
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library ieee, work;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.std_logic_unsigned.all;
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use work.tdc_pkg.all;
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entity dummy_tdc is
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port(
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tdc_i : out t_tdc_in);
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end entity dummy_tdc;
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--------------------------------------------------------------------------------
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-- Object : Architecture work.dummy_tdc.rtl
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-- Last modified : Thu Jul 25 10:01:05 2013.
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--------------------------------------------------------------------------------
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architecture rtl of dummy_tdc is
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begin
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-- tdc_i.clk_p <= '0';
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-- tdc_i.clk_n <= '1';
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tdc_i.s <= (others => '0');
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tdc_i.s_n <= (others => '1');
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tdc_i.sw <= '0';
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tdc_i.ss2 <= '0';
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end architecture rtl ; -- of dummy_tdc
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--------------------------------------------------------------------------------
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-- Object : Entity work.dummy_aes
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-- Last modified : Mon Jul 01 11:54:44 2013.
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--------------------------------------------------------------------------------
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library ieee, work;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.std_logic_unsigned.all;
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use work.aes_pkg.all;
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entity dummy_aes is
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port(
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aes_i : out t_aes_in);
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end entity dummy_aes;
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--------------------------------------------------------------------------------
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-- Object : Architecture work.dummy_aes.rtl
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-- Last modified : Mon Jul 01 11:54:44 2013.
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--------------------------------------------------------------------------------
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architecture rtl of dummy_aes is
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begin
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aes_i.audio_in <= '0';
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aes_i.fifo_rd <= '0';
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end architecture rtl ; -- of dummy_aes
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--------------------------------------------------------------------------------
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-- Object : Entity work.tri_state
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-- Last modified : Fri Jun 28 14:46:56 2013.
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--------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.std_logic_unsigned.all;
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entity tri_state is
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port(
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i : in std_logic;
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o : out std_logic;
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oen : in std_logic);
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end entity tri_state;
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--------------------------------------------------------------------------------
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-- Object : Architecture work.tri_state.structure
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-- Last modified : Fri Jun 28 14:46:56 2013.
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--------------------------------------------------------------------------------
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architecture structure of tri_state is
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begin
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o <= i when (oen = '0') else 'Z';
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end architecture structure ; -- of tri_state
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--------------------------------------------------------------------------------
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-- Object : Entity work.DummySlave
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-- Last modified : Tue Jan 15 14:25:05 2013.
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--------------------------------------------------------------------------------
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library ieee, work;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.std_logic_unsigned.all;
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use work.wishbone_pkg.all;
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entity DummySlave is
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port(
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slave_i : out t_wishbone_slave_in;
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slave_o : out t_wishbone_slave_out);
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end entity DummySlave;
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--------------------------------------------------------------------------------
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-- Object : Architecture work.DummySlave.a0
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-- Last modified : Tue Jan 15 14:25:05 2013.
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--------------------------------------------------------------------------------
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architecture a0 of DummySlave is
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begin
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-- Slave input wishbone signals
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slave_i.cyc <= '0';
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slave_i.stb <= '0';
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slave_i.adr <= (Others => '0');
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slave_i.sel <= "0000";
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slave_i.we <= '0';
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slave_i.dat <= (Others => '0');
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-- Slave output wishbone signals
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slave_o.ack <= '0';
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slave_o.err <= '0';
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slave_o.rty <= '0';
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slave_o.stall <= '0';
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slave_o.int <= '0';
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slave_o.dat <= (Others => '0');
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end architecture a0 ; -- of DummySlave
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--------------------------------------------------------------------------------
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-- Object : Entity work.Dum_mnic
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-- Last modified : Tue Jan 15 14:28:09 2013.
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--------------------------------------------------------------------------------
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library ieee, work;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.std_logic_unsigned.all;
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use work.genram_pkg.all;
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use work.wishbone_pkg.all;
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entity Dum_mnic is
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generic(
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g_dpram_size : integer := 20480);
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port(
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dpram_wbb_i : out t_wishbone_slave_in;
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dpram_wbb_o : in t_wishbone_slave_out);
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end entity Dum_mnic;
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--------------------------------------------------------------------------------
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-- Object : Architecture work.Dum_mnic.a0
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-- Last modified : Tue Jan 15 14:28:09 2013.
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--------------------------------------------------------------------------------
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architecture a0 of Dum_mnic is
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constant c_mnic_memsize_log2 : integer := f_log2_size(g_dpram_size);
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begin
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dpram_wbb_i.cyc <= '1';
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dpram_wbb_i.stb <= '1';
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dpram_wbb_i.adr(c_mnic_memsize_log2-1 downto 0) <= "000000000000000";
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dpram_wbb_i.sel <= "1111";
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dpram_wbb_i.we <= '0';
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dpram_wbb_i.dat <= "00000000000000000000000000000000";
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-- mnic_mem_data_i <= dpram_wbb_o.dat;
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end architecture a0 ; -- of Dum_mnic
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--------------------------------------------------------------------------------
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-- Object : Entity work.lm32_2nd
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-- Last modified : Fri Sep 20 13:18:24 2013.
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--------------------------------------------------------------------------------
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library ieee, work;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.std_logic_unsigned.all;
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use work.wishbone_pkg.all;
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use work.endpoint_pkg.all;
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use work.wrcore_pkg.all;
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use work.lm32_2nd_pkg.all;
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use work.tdc_pkg.all;
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use work.aes_pkg.all;
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entity lm32_2nd is
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generic(
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g_dpram_size : natural := 20480;
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g_date_id : integer := 0;
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g_revision_id : integer := 0);
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port(
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GPIO_LED : out std_logic_vector(6 downto 0);
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aes_i : in t_aes_in;
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aes_o : out t_aes_out;
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clk_sys_i : in std_logic;
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irq_i : in std_logic_vector(31 downto 0);
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pad_cs_o : out std_logic;
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pad_miso_i : in std_logic;
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pad_mosi_o : out std_logic;
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pad_sclk_o : out std_logic;
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rst_n_i : in std_logic;
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sRx : in std_logic;
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sTx : out std_logic;
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scl1 : inout std_logic;
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scl2 : inout std_logic;
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sda1 : inout std_logic;
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sda2 : inout std_logic;
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tdc_i : in t_tdc_in;
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tdc_o : out t_tdc_out);
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end entity lm32_2nd;
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--------------------------------------------------------------------------------
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-- Object : Architecture work.lm32_2nd.a0
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-- Last modified : Fri Sep 20 13:18:24 2013.
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--------------------------------------------------------------------------------
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architecture a0 of lm32_2nd is
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-----------------------------------------------------------------------------
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--WB Secondary Crossbar
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-----------------------------------------------------------------------------
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constant c_secbar_layout : t_sdb_record_array(15 downto 0) :=
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(0 => f_sdb_embed_device(c_wrc_periph1_sdb, x"00000000"), -- UART
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1 => f_sdb_embed_device(c_tdc_sdb, x"00000100"), -- TDCs
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2 => f_sdb_embed_device(c_aes_sdb, x"00000200"), -- AES
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3 => f_sdb_embed_device(c_wrc_periph4_sdb, x"00000300"), -- GPIO
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4 => f_sdb_embed_device(c_wrc_periph5_sdb, x"00000400"), -- SPI
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5 => f_sdb_embed_device(c_wrc_periph6_sdb, x"00000500"), -- I2C1
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6 => f_sdb_embed_device(c_wrc_periph6_sdb, x"00000600"), -- I2C2
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7 => f_sdb_embed_device(c_wrc_periph7_sdb, x"00000700"), -- Timer
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8 => f_sdb_embed_device(c_wrc_periph8_sdb, x"00000800"), -- DATE_REVISION_ID
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9 => f_sdb_embed_device(c_wrc_periph3_sdb, x"00000900"),
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10 => f_sdb_embed_device(c_wrc_periph3_sdb, x"00000A00"),
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11 => f_sdb_embed_device(c_wrc_periph3_sdb, x"00000B00"),
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12 => f_sdb_embed_device(c_wrc_periph3_sdb, x"00000C00"),
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13 => f_sdb_embed_device(c_wrc_periph3_sdb, x"00000D00"),
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14 => f_sdb_embed_device(c_wrc_periph3_sdb, x"00000E00"),
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15 => f_sdb_embed_device(c_wrc_periph3_sdb, x"00000F00")
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);
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constant c_secbar_sdb_address : t_wishbone_address := x"00001000";
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constant c_secbar_bridge_sdb : t_sdb_bridge :=
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f_xwb_bridge_layout_sdb(true, c_secbar_layout, c_secbar_sdb_address);
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-----------------------------------------------------------------------------
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--WB intercon
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-----------------------------------------------------------------------------
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constant c_layout : t_sdb_record_array(1 downto 0) :=
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(0 => f_sdb_embed_device(f_xwb_dpram(g_dpram_size), x"00000000"),
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1 => f_sdb_embed_bridge(c_secbar_bridge_sdb, x"00020000"));
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constant c_sdb_address : t_wishbone_address := x"00030000";
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signal cbar_slave_i : t_wishbone_slave_in_array(2 downto 0);
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signal cbar_slave_o : t_wishbone_slave_out_array(2 downto 0);
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signal cbar_master_i : t_wishbone_master_in_array(1 downto 0);
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signal cbar_master_o : t_wishbone_master_out_array(1 downto 0);
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signal slave2_o : t_wishbone_slave_out;
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signal dpram_wbb_i : t_wishbone_slave_in;
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signal secbar_master_i : t_wishbone_master_in_array(15 downto 0);
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signal secbar_master_o : t_wishbone_master_out_array(15 downto 0);
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signal xwb_sdb_crossbar_slave_i : t_wishbone_slave_in_array(0 downto 0);
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signal xwb_sdb_crossbar_slave_o : t_wishbone_slave_out_array(0 downto 0);
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signal scl_pad_o : std_logic;
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signal scl_padoen_o : std_logic;
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signal sda_pad_o : std_logic;
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signal sda_padoen_o : std_logic;
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signal Net_21 : std_logic;
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signal Net_22 : std_logic;
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signal Net_24 : std_logic;
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signal Net_25 : std_logic;
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signal u18_pad_cs_o : std_logic_vector(7 downto 0);
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component Dum_mnic
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generic(
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g_dpram_size : integer := 20480);
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port(
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dpram_wbb_i : out t_wishbone_slave_in;
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dpram_wbb_o : in t_wishbone_slave_out);
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end component Dum_mnic;
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component DummySlave
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port(
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slave_i : out t_wishbone_slave_in;
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slave_o : out t_wishbone_slave_out);
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end component DummySlave;
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component xwb_lm32
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generic(
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g_profile : string := "medium_icache_debug");
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port(
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clk_sys_i : in std_logic;
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dwb_i : in t_wishbone_master_in;
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dwb_o : out t_wishbone_master_out;
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irq_i : in std_logic_vector(31 downto 0);
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iwb_i : in t_wishbone_master_in;
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iwb_o : out t_wishbone_master_out;
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rst_n_i : in std_logic);
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end component xwb_lm32;
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component xwb_dpram
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generic(
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g_init_file : string := "";
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g_must_have_init_file : boolean := true;
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g_slave2_interface_mode : t_wishbone_interface_mode := PIPELINED;
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g_slave2_granularity : t_wishbone_address_granularity := WORD;
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g_size : natural := 16384;
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g_slave1_interface_mode : t_wishbone_interface_mode := PIPELINED;
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g_slave1_granularity : t_wishbone_address_granularity := WORD);
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port(
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clk_sys_i : in std_logic;
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rst_n_i : in std_logic;
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slave1_i : in t_wishbone_slave_in;
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slave1_o : out t_wishbone_slave_out;
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slave2_i : in t_wishbone_slave_in;
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slave2_o : out t_wishbone_slave_out);
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end component xwb_dpram;
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component xwb_sdb_crossbar
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generic(
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g_num_masters : integer := 3;
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g_registered : boolean := true;
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g_layout : t_sdb_record_array;
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g_num_slaves : integer := 2;
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g_wraparound : boolean := true;
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g_sdb_addr : t_wishbone_address := x"00000000");
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port(
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clk_sys_i : in std_logic;
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master_i : in t_wishbone_master_in_array(g_num_slaves-1 downto 0);
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master_o : out t_wishbone_master_out_array(g_num_slaves-1 downto 0);
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rst_n_i : in std_logic;
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slave_i : in t_wishbone_slave_in_array(g_num_masters-1 downto 0);
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slave_o : out t_wishbone_slave_out_array(g_num_masters-1 downto 0));
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end component xwb_sdb_crossbar;
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component xwb_simple_uart
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generic(
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g_with_virtual_uart : boolean := False;
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g_with_physical_uart : boolean := True;
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g_interface_mode : t_wishbone_interface_mode := CLASSIC;
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g_address_granularity : t_wishbone_address_granularity := WORD);
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port(
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clk_sys_i : in std_logic;
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rst_n_i : in std_logic;
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slave_i : in t_wishbone_slave_in;
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slave_o : out t_wishbone_slave_out;
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uart_rxd_i : in std_logic;
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uart_txd_o : out std_logic);
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end component xwb_simple_uart;
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component xwb_tics
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generic(
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g_interface_mode : t_wishbone_interface_mode := CLASSIC;
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g_address_granularity : t_wishbone_address_granularity := WORD;
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g_period : integer := 100);
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port(
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clk_sys_i : in std_logic;
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desc_o : out t_wishbone_device_descriptor;
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rst_n_i : in std_logic;
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slave_i : in t_wishbone_slave_in;
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slave_o : out t_wishbone_slave_out);
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end component xwb_tics;
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component xwb_gpio_port
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generic(
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g_interface_mode : t_wishbone_interface_mode := CLASSIC;
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g_address_granularity : t_wishbone_address_granularity := WORD;
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g_num_pins : natural range 1 to 256 := 32;
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g_with_builtin_tristates : boolean := false);
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port(
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clk_sys_i : in std_logic;
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desc_o : out t_wishbone_device_descriptor;
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gpio_b : inout std_logic_vector(g_num_pins-1 downto 0);
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gpio_in_i : in std_logic_vector(g_num_pins-1 downto 0);
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gpio_oen_o : out std_logic_vector(g_num_pins-1 downto 0);
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gpio_out_o : out std_logic_vector(g_num_pins-1 downto 0);
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rst_n_i : in std_logic;
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slave_i : in t_wishbone_slave_in;
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slave_o : out t_wishbone_slave_out);
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end component xwb_gpio_port;
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component xwb_i2c_master
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generic(
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g_interface_mode : t_wishbone_interface_mode := CLASSIC;
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g_address_granularity : t_wishbone_address_granularity := WORD);
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port(
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clk_sys_i : in std_logic;
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desc_o : out t_wishbone_device_descriptor;
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rst_n_i : in std_logic;
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scl_pad_i : in std_logic;
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scl_pad_o : out std_logic;
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scl_padoen_o : out std_logic;
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sda_pad_i : in std_logic;
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sda_pad_o : out std_logic;
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sda_padoen_o : out std_logic;
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slave_i : in t_wishbone_slave_in;
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slave_o : out t_wishbone_slave_out);
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end component xwb_i2c_master;
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component tri_state
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port(
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i : in std_logic;
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o : out std_logic;
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oen : in std_logic);
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end component tri_state;
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component xwb_date_rev_id
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generic(
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g_date_id : integer := 0;
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g_revision_id : integer := 0;
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|
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
|
|
g_address_granularity : t_wishbone_address_granularity := WORD);
|
|
port(
|
|
clk_sys_i : in std_logic;
|
|
rst_n_i : in std_logic;
|
|
slave_i : in t_wishbone_slave_in;
|
|
slave_o : out t_wishbone_slave_out);
|
|
end component xwb_date_rev_id;
|
|
|
|
component xwb_spi
|
|
generic(
|
|
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
|
|
g_address_granularity : t_wishbone_address_granularity := WORD);
|
|
port(
|
|
clk_sys_i : in std_logic;
|
|
desc_o : out t_wishbone_device_descriptor;
|
|
pad_cs_o : out std_logic_vector(7 downto 0);
|
|
pad_miso_i : in std_logic;
|
|
pad_mosi_o : out std_logic;
|
|
pad_sclk_o : out std_logic;
|
|
rst_n_i : in std_logic;
|
|
slave_i : in t_wishbone_slave_in;
|
|
slave_o : out t_wishbone_slave_out);
|
|
end component xwb_spi;
|
|
|
|
component xwb_tdc
|
|
generic(
|
|
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
|
|
g_address_granularity : t_wishbone_address_granularity := WORD;
|
|
g_channels : integer := 31);
|
|
port(
|
|
clk_sys_i : in std_logic;
|
|
desc_o : out t_wishbone_device_descriptor;
|
|
rst_n_i : in std_logic;
|
|
slave_i : in t_wishbone_slave_in;
|
|
slave_o : out t_wishbone_slave_out;
|
|
tdc_i : in t_tdc_in;
|
|
tdc_o : out t_tdc_out);
|
|
end component xwb_tdc;
|
|
|
|
component xwb_aes
|
|
generic(
|
|
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
|
|
g_address_granularity : t_wishbone_address_granularity := WORD;
|
|
g_word_size : integer := 64);
|
|
port(
|
|
aes_i : in t_aes_in;
|
|
aes_o : out t_aes_out;
|
|
clk_sys_i : in std_logic;
|
|
desc_o : out t_wishbone_device_descriptor;
|
|
rst_n_i : in std_logic;
|
|
slave_i : in t_wishbone_slave_in;
|
|
slave_o : out t_wishbone_slave_out);
|
|
end component xwb_aes;
|
|
|
|
begin
|
|
--cbar_slave(2) ought to be
|
|
--connected to the PCI-express brigde
|
|
--WB_CON
|
|
--WB_SECONDARY_CON
|
|
--period 1 ms
|
|
--@ clk_sys_i = 125 Mhz => g_period = 125000
|
|
--@ clk_sys_i = 62.5 Mhz => g_period = 62500
|
|
pad_cs_o <= u18_pad_cs_o(0);
|
|
u6: Dum_mnic
|
|
generic map(
|
|
g_dpram_size => g_dpram_size)
|
|
port map(
|
|
dpram_wbb_i => dpram_wbb_i,
|
|
dpram_wbb_o => slave2_o);
|
|
|
|
u2: DummySlave
|
|
port map(
|
|
slave_i => cbar_slave_i(2),
|
|
slave_o => cbar_slave_o(2));
|
|
|
|
u0: xwb_lm32
|
|
generic map(
|
|
g_profile => "medium_icache_debug")
|
|
port map(
|
|
clk_sys_i => clk_sys_i,
|
|
dwb_i => cbar_slave_o(0),
|
|
dwb_o => cbar_slave_i(0),
|
|
irq_i => irq_i,
|
|
iwb_i => cbar_slave_o(1),
|
|
iwb_o => cbar_slave_i(1),
|
|
rst_n_i => rst_n_i);
|
|
|
|
u4: xwb_dpram
|
|
generic map(
|
|
g_init_file => "lm32_memory.ldr",
|
|
g_must_have_init_file => true,
|
|
g_slave2_interface_mode => PIPELINED,
|
|
g_slave2_granularity => WORD,
|
|
g_size => g_dpram_size,
|
|
g_slave1_interface_mode => PIPELINED,
|
|
g_slave1_granularity => BYTE)
|
|
port map(
|
|
clk_sys_i => clk_sys_i,
|
|
rst_n_i => rst_n_i,
|
|
slave1_i => cbar_master_o(0),
|
|
slave1_o => cbar_master_i(0),
|
|
slave2_i => dpram_wbb_i,
|
|
slave2_o => slave2_o);
|
|
|
|
u1: xwb_sdb_crossbar
|
|
generic map(
|
|
g_num_masters => 3,
|
|
g_registered => true,
|
|
g_layout => c_layout,
|
|
g_num_slaves => 2,
|
|
g_wraparound => true,
|
|
g_sdb_addr => c_sdb_address)
|
|
port map(
|
|
clk_sys_i => clk_sys_i,
|
|
master_i => cbar_master_i,
|
|
master_o => cbar_master_o,
|
|
rst_n_i => rst_n_i,
|
|
slave_i => cbar_slave_i,
|
|
slave_o => cbar_slave_o);
|
|
|
|
u9: xwb_sdb_crossbar
|
|
generic map(
|
|
g_num_masters => 1,
|
|
g_registered => true,
|
|
g_layout => c_secbar_layout,
|
|
g_num_slaves => 16,
|
|
g_wraparound => true,
|
|
g_sdb_addr => c_secbar_sdb_address)
|
|
port map(
|
|
clk_sys_i => clk_sys_i,
|
|
master_i => secbar_master_i,
|
|
master_o => secbar_master_o,
|
|
rst_n_i => rst_n_i,
|
|
slave_i => xwb_sdb_crossbar_slave_i,
|
|
slave_o => xwb_sdb_crossbar_slave_o);
|
|
|
|
u12: xwb_simple_uart
|
|
generic map(
|
|
g_with_virtual_uart => False,
|
|
g_with_physical_uart => True,
|
|
g_interface_mode => PIPELINED,
|
|
g_address_granularity => BYTE)
|
|
port map(
|
|
clk_sys_i => clk_sys_i,
|
|
rst_n_i => rst_n_i,
|
|
slave_i => secbar_master_o(0),
|
|
slave_o => secbar_master_i(0),
|
|
uart_rxd_i => sRx,
|
|
uart_txd_o => sTx);
|
|
|
|
u3: xwb_tics
|
|
generic map(
|
|
g_interface_mode => PIPELINED,
|
|
g_address_granularity => BYTE,
|
|
g_period => 62500)
|
|
port map(
|
|
clk_sys_i => clk_sys_i,
|
|
desc_o => open,
|
|
rst_n_i => rst_n_i,
|
|
slave_i => secbar_master_o(7),
|
|
slave_o => secbar_master_i(7));
|
|
|
|
u5: xwb_gpio_port
|
|
generic map(
|
|
g_interface_mode => PIPELINED,
|
|
g_address_granularity => BYTE,
|
|
g_num_pins => 7,
|
|
g_with_builtin_tristates => FALSE)
|
|
port map(
|
|
clk_sys_i => clk_sys_i,
|
|
desc_o => open,
|
|
gpio_b => open,
|
|
gpio_in_i => "0000000",
|
|
gpio_oen_o => open,
|
|
gpio_out_o => GPIO_LED,
|
|
rst_n_i => rst_n_i,
|
|
slave_i => secbar_master_o(3),
|
|
slave_o => secbar_master_i(3));
|
|
|
|
u7: xwb_i2c_master
|
|
generic map(
|
|
g_interface_mode => PIPELINED,
|
|
g_address_granularity => BYTE)
|
|
port map(
|
|
clk_sys_i => clk_sys_i,
|
|
desc_o => open,
|
|
rst_n_i => rst_n_i,
|
|
scl_pad_i => scl1,
|
|
scl_pad_o => scl_pad_o,
|
|
scl_padoen_o => scl_padoen_o,
|
|
sda_pad_i => sda1,
|
|
sda_pad_o => sda_pad_o,
|
|
sda_padoen_o => sda_padoen_o,
|
|
slave_i => secbar_master_o(5),
|
|
slave_o => secbar_master_i(5));
|
|
|
|
u8: tri_state
|
|
port map(
|
|
i => scl_pad_o,
|
|
o => scl1,
|
|
oen => scl_padoen_o);
|
|
|
|
u10: tri_state
|
|
port map(
|
|
i => sda_pad_o,
|
|
o => sda1,
|
|
oen => sda_padoen_o);
|
|
|
|
u14: xwb_i2c_master
|
|
generic map(
|
|
g_interface_mode => PIPELINED,
|
|
g_address_granularity => BYTE)
|
|
port map(
|
|
clk_sys_i => clk_sys_i,
|
|
desc_o => open,
|
|
rst_n_i => rst_n_i,
|
|
scl_pad_i => scl2,
|
|
scl_pad_o => Net_21,
|
|
scl_padoen_o => Net_22,
|
|
sda_pad_i => sda2,
|
|
sda_pad_o => Net_24,
|
|
sda_padoen_o => Net_25,
|
|
slave_i => secbar_master_o(6),
|
|
slave_o => secbar_master_i(6));
|
|
|
|
u16: tri_state
|
|
port map(
|
|
i => Net_21,
|
|
o => scl2,
|
|
oen => Net_22);
|
|
|
|
u17: tri_state
|
|
port map(
|
|
i => Net_24,
|
|
o => sda2,
|
|
oen => Net_25);
|
|
|
|
u15: xwb_date_rev_id
|
|
generic map(
|
|
g_date_id => g_date_id,
|
|
g_revision_id => g_revision_id,
|
|
g_interface_mode => CLASSIC,
|
|
g_address_granularity => WORD)
|
|
port map(
|
|
clk_sys_i => clk_sys_i,
|
|
rst_n_i => rst_n_i,
|
|
slave_i => secbar_master_o(8),
|
|
slave_o => secbar_master_i(8));
|
|
|
|
u18: xwb_spi
|
|
generic map(
|
|
g_interface_mode => PIPELINED,
|
|
g_address_granularity => BYTE)
|
|
port map(
|
|
clk_sys_i => clk_sys_i,
|
|
desc_o => open,
|
|
pad_cs_o => u18_pad_cs_o,
|
|
pad_miso_i => pad_miso_i,
|
|
pad_mosi_o => pad_mosi_o,
|
|
pad_sclk_o => pad_sclk_o,
|
|
rst_n_i => rst_n_i,
|
|
slave_i => secbar_master_o(4),
|
|
slave_o => secbar_master_i(4));
|
|
|
|
u11: xwb_tdc
|
|
generic map(
|
|
g_interface_mode => PIPELINED,
|
|
g_address_granularity => BYTE,
|
|
g_channels => c_tdc_channels)
|
|
port map(
|
|
clk_sys_i => clk_sys_i,
|
|
desc_o => open,
|
|
rst_n_i => rst_n_i,
|
|
slave_i => secbar_master_o(1),
|
|
slave_o => secbar_master_i(1),
|
|
tdc_i => tdc_i,
|
|
tdc_o => tdc_o);
|
|
|
|
u19: xwb_aes
|
|
generic map(
|
|
g_interface_mode => PIPELINED,
|
|
g_address_granularity => BYTE,
|
|
g_word_size => c_aes_word_size)
|
|
port map(
|
|
aes_i => aes_i,
|
|
aes_o => aes_o,
|
|
clk_sys_i => clk_sys_i,
|
|
desc_o => open,
|
|
rst_n_i => rst_n_i,
|
|
slave_i => secbar_master_o(2),
|
|
slave_o => secbar_master_i(2));
|
|
|
|
u13: DummySlave
|
|
port map(
|
|
slave_i => open,
|
|
slave_o => secbar_master_i(9));
|
|
|
|
u20: DummySlave
|
|
port map(
|
|
slave_i => open,
|
|
slave_o => secbar_master_i(10));
|
|
|
|
u21: DummySlave
|
|
port map(
|
|
slave_i => open,
|
|
slave_o => secbar_master_i(11));
|
|
|
|
u22: DummySlave
|
|
port map(
|
|
slave_i => open,
|
|
slave_o => secbar_master_i(12));
|
|
|
|
u23: DummySlave
|
|
port map(
|
|
slave_i => open,
|
|
slave_o => secbar_master_i(13));
|
|
|
|
u24: DummySlave
|
|
port map(
|
|
slave_i => open,
|
|
slave_o => secbar_master_i(14));
|
|
|
|
u25: DummySlave
|
|
port map(
|
|
slave_i => open,
|
|
slave_o => secbar_master_i(15));
|
|
|
|
|
|
xwb_sdb_crossbar_slave_i(0) <= cbar_master_o(1);
|
|
cbar_master_i(1) <= xwb_sdb_crossbar_slave_o(0);
|
|
end architecture a0 ; -- of lm32_2nd
|
|
|
|
--------------------------------------------------------------------------------
|
|
-- Object : Entity work.Reg1NoRst
|
|
-- Last modified : Mon Jan 14 15:05:41 2013.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
|
|
library ieee;
|
|
use ieee.std_logic_1164.all;
|
|
use ieee.numeric_std.all;
|
|
use ieee.std_logic_unsigned.all;
|
|
|
|
entity Reg1NoRst is
|
|
port(
|
|
Clk : in std_logic;
|
|
D : in std_logic;
|
|
O : out std_logic := '0';
|
|
O_n : out std_logic);
|
|
end entity Reg1NoRst;
|
|
|
|
--------------------------------------------------------------------------------
|
|
-- Object : Architecture work.Reg1NoRst.rtl
|
|
-- Last modified : Mon Jan 14 15:05:41 2013.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
architecture rtl of Reg1NoRst is
|
|
|
|
begin
|
|
Process (Clk)
|
|
Begin
|
|
If Rising_Edge(Clk) Then
|
|
O <= D;
|
|
O_n <= Not D;
|
|
End If;
|
|
End Process;
|
|
end architecture rtl ; -- of Reg1NoRst
|
|
|
|
--------------------------------------------------------------------------------
|
|
-- Object : Entity work.MetaStabelizer
|
|
-- Last modified : Mon Jan 14 15:05:19 2013.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
|
|
library ieee;
|
|
use ieee.std_logic_1164.all;
|
|
use ieee.numeric_std.all;
|
|
use ieee.std_logic_unsigned.all;
|
|
|
|
entity MetaStabelizer is
|
|
port(
|
|
Clk : in std_logic;
|
|
D : in std_logic;
|
|
O : out std_logic;
|
|
O_n : out std_logic);
|
|
end entity MetaStabelizer;
|
|
|
|
--------------------------------------------------------------------------------
|
|
-- Object : Architecture work.MetaStabelizer.rtl
|
|
-- Last modified : Mon Jan 14 15:05:19 2013.
|
|
--------------------------------------------------------------------------------
|
|
|
|
architecture rtl of MetaStabelizer is
|
|
|
|
signal O_net : std_logic := '0';
|
|
|
|
component Reg1NoRst
|
|
port(
|
|
Clk : in std_logic;
|
|
D : in std_logic;
|
|
O : out std_logic := '0';
|
|
O_n : out std_logic);
|
|
end component Reg1NoRst;
|
|
|
|
begin
|
|
u0: Reg1NoRst
|
|
port map(
|
|
Clk => Clk,
|
|
D => D,
|
|
O => O_net,
|
|
O_n => open);
|
|
|
|
u1: Reg1NoRst
|
|
port map(
|
|
Clk => Clk,
|
|
D => O_net,
|
|
O => O,
|
|
O_n => O_n);
|
|
|
|
end architecture rtl ; -- of MetaStabelizer
|
|
|
|
--------------------------------------------------------------------------------
|
|
-- Object : Entity work.Counter
|
|
-- Last modified : Mon Nov 19 11:51:35 2012.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
|
|
library ieee;
|
|
use ieee.std_logic_1164.all;
|
|
use ieee.numeric_std.all;
|
|
use ieee.std_logic_unsigned.all;
|
|
|
|
entity Counter is
|
|
port(
|
|
Clk : in std_logic;
|
|
Q : out std_logic_vector(31 downto 0);
|
|
Rst : in std_logic);
|
|
end entity Counter;
|
|
|
|
--------------------------------------------------------------------------------
|
|
-- Object : Architecture work.Counter.rtl
|
|
-- Last modified : Mon Nov 19 11:51:35 2012.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
architecture rtl of Counter is
|
|
|
|
begin
|
|
Process (Clk, Rst)
|
|
Variable Count: Unsigned(31 downto 0) := (Others => '0');
|
|
Begin
|
|
If Rst = '1' Then
|
|
Count := (Others => '0');
|
|
ElsIf Rising_Edge(Clk) Then
|
|
Count := Count + 1;
|
|
End If;
|
|
Q <= Std_Logic_Vector (Count);
|
|
End Process;
|
|
end architecture rtl ; -- of Counter
|
|
|
|
--------------------------------------------------------------------------------
|
|
-- Object : Entity work.fpga
|
|
-- Last modified : Fri Jul 05 14:23:51 2013.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
|
|
library ieee, work;
|
|
use ieee.std_logic_1164.all;
|
|
use ieee.numeric_std.all;
|
|
use ieee.std_logic_unsigned.all;
|
|
use work.wishbone_pkg.all;
|
|
use work.endpoint_pkg.all;
|
|
use work.wrcore_pkg.all;
|
|
use work.aes_pkg.all;
|
|
use work.tdc_pkg.all;
|
|
|
|
entity fpga is
|
|
generic(
|
|
g_date_id : integer := 0;
|
|
g_revision_id : integer := 0;
|
|
g_dpram_size : natural := 20480);
|
|
port(
|
|
Blink : out std_logic;
|
|
ClkI_n : in std_logic;
|
|
ClkI_p : in std_logic;
|
|
GPIO_LED : out std_logic_vector(6 downto 0);
|
|
RST_I : in std_logic;
|
|
Spy2 : out std_logic;
|
|
Spy3 : out std_logic;
|
|
irq_0 : in std_logic;
|
|
irq_1 : in std_logic;
|
|
pad_cs_o : out std_logic;
|
|
pad_miso_i : in std_logic;
|
|
pad_mosi_o : out std_logic;
|
|
pad_sclk_o : out std_logic;
|
|
sRx : in std_logic;
|
|
sTx : out std_logic;
|
|
scl1 : inout std_logic;
|
|
scl2 : inout std_logic;
|
|
sda1 : inout std_logic;
|
|
sda2 : inout std_logic);
|
|
end entity fpga;
|
|
|
|
--------------------------------------------------------------------------------
|
|
-- Object : Architecture work.fpga.a0
|
|
-- Last modified : Fri Jul 05 14:23:51 2013.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
library UNISIM;
|
|
use UNISIM.IBUFDS_GTE2;
|
|
|
|
architecture a0 of fpga is
|
|
|
|
signal Net_0 : std_logic_vector(31 downto 0);
|
|
signal u5_O : std_logic;
|
|
signal O_n : std_logic;
|
|
signal u7_O : std_logic;
|
|
signal Spy3_net : std_logic;
|
|
signal clk_62_5_o : std_logic;
|
|
signal aes_i : t_aes_in;
|
|
signal tdc_i : t_tdc_in;
|
|
signal irq_i : std_logic_vector(31 downto 0);
|
|
|
|
component Counter
|
|
port(
|
|
Clk : in std_logic;
|
|
Q : out std_logic_vector(31 downto 0);
|
|
Rst : in std_logic);
|
|
end component Counter;
|
|
|
|
component MetaStabelizer
|
|
port(
|
|
Clk : in std_logic;
|
|
D : in std_logic;
|
|
O : out std_logic;
|
|
O_n : out std_logic);
|
|
end component MetaStabelizer;
|
|
|
|
component IBUFDS_GTE2
|
|
port(
|
|
CEB : in std_logic;
|
|
I : in std_logic;
|
|
IB : in std_logic;
|
|
O : out std_logic;
|
|
ODIV2 : out std_logic);
|
|
end component IBUFDS_GTE2;
|
|
|
|
component lm32_2nd
|
|
generic(
|
|
g_dpram_size : natural := 20480;
|
|
g_date_id : integer := 0;
|
|
g_revision_id : integer := 0);
|
|
port(
|
|
GPIO_LED : out std_logic_vector(6 downto 0);
|
|
aes_i : in t_aes_in;
|
|
aes_o : out t_aes_out;
|
|
clk_sys_i : in std_logic;
|
|
irq_i : in std_logic_vector(31 downto 0);
|
|
pad_cs_o : out std_logic;
|
|
pad_miso_i : in std_logic;
|
|
pad_mosi_o : out std_logic;
|
|
pad_sclk_o : out std_logic;
|
|
rst_n_i : in std_logic;
|
|
sRx : in std_logic;
|
|
sTx : out std_logic;
|
|
scl1 : inout std_logic;
|
|
scl2 : inout std_logic;
|
|
sda1 : inout std_logic;
|
|
sda2 : inout std_logic;
|
|
tdc_i : in t_tdc_in;
|
|
tdc_o : out t_tdc_out);
|
|
end component lm32_2nd;
|
|
|
|
component cmp_sys_clk_pll
|
|
port(
|
|
clk_125_o : out std_logic;
|
|
clk_62_5_o : out std_logic;
|
|
clk_i : in std_logic;
|
|
locked_o : out std_logic;
|
|
rst_i : in std_logic);
|
|
end component cmp_sys_clk_pll;
|
|
|
|
component dummy_aes
|
|
port(
|
|
aes_i : out t_aes_in);
|
|
end component dummy_aes;
|
|
|
|
component dummy_tdc
|
|
port(
|
|
tdc_i : out t_tdc_in);
|
|
end component dummy_tdc;
|
|
|
|
component low
|
|
generic(
|
|
n : integer := 8);
|
|
port(
|
|
o : out std_logic_vector(n-1 downto 0));
|
|
end component low;
|
|
|
|
begin
|
|
--This Metastabelizer also synchronizes RST_I
|
|
--to the CLK_I clock domain. Such a synchronous
|
|
--reset may be necessary to avoid asynchronous
|
|
--signal changes on the wb_memory that could
|
|
--trigger false write actions...
|
|
--SGMIICLK_Q0_P (pin G8)
|
|
--SGMIICLK_Q0_N (pin G7)
|
|
--connect to 125 MHz Xtal on KC705
|
|
Blink <= Net_0(24);
|
|
Spy2 <= Net_0(24);
|
|
sTx <= Spy3_net;
|
|
Spy3 <= Spy3_net;
|
|
u3: Counter
|
|
port map(
|
|
Clk => clk_62_5_o,
|
|
Q => Net_0,
|
|
Rst => u7_O);
|
|
|
|
u7: MetaStabelizer
|
|
port map(
|
|
Clk => clk_62_5_o,
|
|
D => RST_I,
|
|
O => u7_O,
|
|
O_n => O_n);
|
|
|
|
u5: IBUFDS_GTE2
|
|
port map(
|
|
CEB => '0',
|
|
I => ClkI_p,
|
|
IB => ClkI_n,
|
|
O => u5_O,
|
|
ODIV2 => open);
|
|
|
|
u0: lm32_2nd
|
|
generic map(
|
|
g_dpram_size => g_dpram_size,
|
|
g_date_id => g_date_id,
|
|
g_revision_id => g_revision_id)
|
|
port map(
|
|
GPIO_LED => GPIO_LED,
|
|
aes_i => aes_i,
|
|
aes_o => open,
|
|
clk_sys_i => clk_62_5_o,
|
|
irq_i => irq_i,
|
|
pad_cs_o => pad_cs_o,
|
|
pad_miso_i => pad_miso_i,
|
|
pad_mosi_o => pad_mosi_o,
|
|
pad_sclk_o => pad_sclk_o,
|
|
rst_n_i => O_n,
|
|
sRx => sRx,
|
|
sTx => Spy3_net,
|
|
scl1 => scl1,
|
|
scl2 => scl2,
|
|
sda1 => sda1,
|
|
sda2 => sda2,
|
|
tdc_i => tdc_i,
|
|
tdc_o => open);
|
|
|
|
u1: cmp_sys_clk_pll
|
|
port map(
|
|
clk_125_o => open,
|
|
clk_62_5_o => clk_62_5_o,
|
|
clk_i => u5_O,
|
|
locked_o => open,
|
|
rst_i => '0');
|
|
|
|
u2: dummy_aes
|
|
port map(
|
|
aes_i => aes_i);
|
|
|
|
u4: dummy_tdc
|
|
port map(
|
|
tdc_i => tdc_i);
|
|
|
|
u6: MetaStabelizer
|
|
port map(
|
|
Clk => clk_62_5_o,
|
|
D => irq_1,
|
|
O => irq_i(1),
|
|
O_n => open);
|
|
|
|
u8: MetaStabelizer
|
|
port map(
|
|
Clk => clk_62_5_o,
|
|
D => irq_0,
|
|
O => irq_i(0),
|
|
O_n => open);
|
|
|
|
u9: low
|
|
generic map(
|
|
n => 30)
|
|
port map(
|
|
o => irq_i(31 downto 2));
|
|
|
|
end architecture a0 ; -- of fpga
|
|
|
|
--------------------------------------------------------------------------------
|
|
-- Object : Entity work.pullup1
|
|
-- Last modified : Fri Jun 28 14:34:47 2013.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
|
|
library ieee;
|
|
use ieee.std_logic_1164.all;
|
|
use ieee.numeric_std.all;
|
|
use ieee.std_logic_unsigned.all;
|
|
|
|
entity pullup1 is
|
|
port(
|
|
o : out std_logic);
|
|
end entity pullup1;
|
|
|
|
--------------------------------------------------------------------------------
|
|
-- Object : Architecture work.pullup1.structure
|
|
-- Last modified : Fri Jun 28 14:34:47 2013.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
architecture structure of pullup1 is
|
|
|
|
begin
|
|
o <= 'H';
|
|
end architecture structure ; -- of pullup1
|
|
|
|
--------------------------------------------------------------------------------
|
|
-- Object : Entity work.SYSCON
|
|
-- Last modified : Fri Oct 19 17:26:59 2012.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
|
|
library ieee;
|
|
use ieee.std_logic_1164.all;
|
|
use ieee.numeric_std.all;
|
|
use ieee.std_logic_unsigned.all;
|
|
|
|
entity SYSCON is
|
|
port(
|
|
ClkI_n : out std_logic;
|
|
ClkI_p : out std_logic;
|
|
RST_I : out std_logic);
|
|
end entity SYSCON;
|
|
|
|
--------------------------------------------------------------------------------
|
|
-- Object : Architecture work.SYSCON.rtl
|
|
-- Last modified : Fri Oct 19 17:26:59 2012.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
architecture rtl of SYSCON is
|
|
|
|
begin
|
|
Process
|
|
-- 200 MHz = 5 ns, 125 MHz = 8 ns, 100 MHz = 10 ns, 27 MHz = 37 ns
|
|
Constant ClockPeriod: Time := 8 ns;
|
|
Variable Clock: Std_Logic;
|
|
-- RST_I is de-asserted after 5 CLK_I cycles
|
|
Variable RstCount: Integer range 0 to 15 := 5;
|
|
Begin
|
|
If now = 0 ns Then
|
|
Clock := '0';
|
|
Else
|
|
Clock := Not Clock;
|
|
If clock = '0' and RstCount > 0 Then
|
|
RstCount := RstCount - 1;
|
|
End If;
|
|
End If;
|
|
|
|
ClkI_p <= Clock;
|
|
ClkI_n <= Not Clock;
|
|
|
|
If RstCount > 0 Then
|
|
RST_I <= '1';
|
|
Else
|
|
RST_I <= '0';
|
|
End If;
|
|
|
|
Wait for ClockPeriod / 2;
|
|
End Process;
|
|
|
|
end architecture rtl ; -- of SYSCON
|
|
|
|
--------------------------------------------------------------------------------
|
|
-- Object : Entity work.SystemTop
|
|
-- Last modified : Fri Jul 05 14:22:50 2013.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
|
|
library ieee;
|
|
use ieee.std_logic_1164.all;
|
|
use ieee.numeric_std.all;
|
|
use ieee.std_logic_unsigned.all;
|
|
|
|
entity SystemTop is
|
|
port(
|
|
Blink : out std_logic;
|
|
GPIO_LED : out std_logic_vector(6 downto 0);
|
|
RST_I : in std_logic;
|
|
Spy2 : out std_logic;
|
|
Spy3 : out std_logic;
|
|
TCK : in std_logic;
|
|
TDI : in std_logic;
|
|
TDO : out std_logic;
|
|
TMS : in std_logic;
|
|
irq_0 : in std_logic;
|
|
irq_1 : in std_logic;
|
|
pad_cs_o : out std_logic;
|
|
pad_miso_i : in std_logic;
|
|
pad_mosi_o : out std_logic;
|
|
pad_sclk_o : out std_logic;
|
|
sRx : in std_logic;
|
|
sTX : out std_logic;
|
|
scl1 : inout std_logic;
|
|
scl2 : inout std_logic;
|
|
sda1 : inout std_logic;
|
|
sda2 : inout std_logic);
|
|
end entity SystemTop;
|
|
|
|
--------------------------------------------------------------------------------
|
|
-- Object : Architecture work.SystemTop.a0
|
|
-- Last modified : Fri Jul 05 14:22:50 2013.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
library UNISIM;
|
|
use UNISIM.JTAG_SIME2_SUBMOD;
|
|
|
|
architecture a0 of SystemTop is
|
|
|
|
signal ClkI_p : std_logic;
|
|
signal ClkI_n : std_logic;
|
|
|
|
component SYSCON
|
|
port(
|
|
ClkI_n : out std_logic;
|
|
ClkI_p : out std_logic;
|
|
RST_I : out std_logic);
|
|
end component SYSCON;
|
|
|
|
component JTAG_SIME2_SUBMOD
|
|
generic(
|
|
PART_NAME : string;
|
|
IRLength : integer := 0);
|
|
port(
|
|
TCK : in std_logic;
|
|
TDI : in std_logic;
|
|
TDO : out std_logic;
|
|
TMS : in std_logic);
|
|
end component JTAG_SIME2_SUBMOD;
|
|
|
|
component pullup1
|
|
port(
|
|
o : out std_logic);
|
|
end component pullup1;
|
|
|
|
component fpga
|
|
generic(
|
|
g_date_id : integer := 0;
|
|
g_revision_id : integer := 0;
|
|
g_dpram_size : natural := 20480);
|
|
port(
|
|
Blink : out std_logic;
|
|
ClkI_n : in std_logic;
|
|
ClkI_p : in std_logic;
|
|
GPIO_LED : out std_logic_vector(6 downto 0);
|
|
RST_I : in std_logic;
|
|
Spy2 : out std_logic;
|
|
Spy3 : out std_logic;
|
|
irq_0 : in std_logic;
|
|
irq_1 : in std_logic;
|
|
pad_cs_o : out std_logic;
|
|
pad_miso_i : in std_logic;
|
|
pad_mosi_o : out std_logic;
|
|
pad_sclk_o : out std_logic;
|
|
sRx : in std_logic;
|
|
sTx : out std_logic;
|
|
scl1 : inout std_logic;
|
|
scl2 : inout std_logic;
|
|
sda1 : inout std_logic;
|
|
sda2 : inout std_logic);
|
|
end component fpga;
|
|
|
|
begin
|
|
u1: SYSCON
|
|
port map(
|
|
ClkI_n => ClkI_n,
|
|
ClkI_p => ClkI_p,
|
|
RST_I => open);
|
|
|
|
u3: JTAG_SIME2_SUBMOD
|
|
generic map(
|
|
PART_NAME => "7k325t",
|
|
IRLength => 6)
|
|
port map(
|
|
TCK => TCK,
|
|
TDI => TDI,
|
|
TDO => TDO,
|
|
TMS => TMS);
|
|
|
|
u2: pullup1
|
|
port map(
|
|
o => sda1);
|
|
|
|
u0: fpga
|
|
generic map(
|
|
g_date_id => 0,
|
|
g_revision_id => 0,
|
|
g_dpram_size => 20480)
|
|
port map(
|
|
Blink => Blink,
|
|
ClkI_n => ClkI_n,
|
|
ClkI_p => ClkI_p,
|
|
GPIO_LED => GPIO_LED,
|
|
RST_I => RST_I,
|
|
Spy2 => Spy2,
|
|
Spy3 => Spy3,
|
|
irq_0 => irq_0,
|
|
irq_1 => irq_1,
|
|
pad_cs_o => pad_cs_o,
|
|
pad_miso_i => pad_miso_i,
|
|
pad_mosi_o => pad_mosi_o,
|
|
pad_sclk_o => pad_sclk_o,
|
|
sRx => sRx,
|
|
sTx => sTX,
|
|
scl1 => scl1,
|
|
scl2 => scl2,
|
|
sda1 => sda1,
|
|
sda2 => sda2);
|
|
|
|
u4: pullup1
|
|
port map(
|
|
o => scl1);
|
|
|
|
u5: pullup1
|
|
port map(
|
|
o => scl2);
|
|
|
|
u6: pullup1
|
|
port map(
|
|
o => sda2);
|
|
|
|
end architecture a0 ; -- of SystemTop
|
|
|
|
--------------------------------------------------------------------------------
|
|
-- Object : Configuration work.SystemTop.Functional
|
|
-- Last modified : Fri Jul 05 14:22:50 2013.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
library work, UNISIM;
|
|
|
|
|
|
configuration Functional of SystemTop is
|
|
for a0
|
|
for u1 : SYSCON
|
|
use entity work.SYSCON(rtl);
|
|
end for;
|
|
for u3 : JTAG_SIME2_SUBMOD
|
|
use entity UNISIM.JTAG_SIME2_SUBMOD(JTAG_SIME2_SUBMOD_V);
|
|
end for;
|
|
for u2 : pullup1
|
|
use entity work.pullup1(structure);
|
|
end for;
|
|
for u0 : fpga
|
|
use entity work.fpga(a0);
|
|
for a0
|
|
for u3 : Counter
|
|
use entity work.Counter(rtl);
|
|
end for;
|
|
for u7 : MetaStabelizer
|
|
use entity work.MetaStabelizer(rtl);
|
|
for rtl
|
|
for u0 : Reg1NoRst
|
|
use entity work.Reg1NoRst(rtl);
|
|
end for;
|
|
for u1 : Reg1NoRst
|
|
use entity work.Reg1NoRst(rtl);
|
|
end for;
|
|
end for;
|
|
end for;
|
|
for u5 : IBUFDS_GTE2
|
|
use entity UNISIM.IBUFDS_GTE2(IBUFDS_GTE2_V);
|
|
end for;
|
|
for u0 : lm32_2nd
|
|
use entity work.lm32_2nd(a0);
|
|
for a0
|
|
for u6 : Dum_mnic
|
|
use entity work.Dum_mnic(a0);
|
|
end for;
|
|
for u2 : DummySlave
|
|
use entity work.DummySlave(a0);
|
|
end for;
|
|
for u0 : xwb_lm32
|
|
use entity work.xwb_lm32(rtl);
|
|
end for;
|
|
for u4 : xwb_dpram
|
|
use entity work.xwb_dpram(struct);
|
|
end for;
|
|
for u1 : xwb_sdb_crossbar
|
|
use entity work.xwb_sdb_crossbar(rtl);
|
|
end for;
|
|
for u9 : xwb_sdb_crossbar
|
|
use entity work.xwb_sdb_crossbar(rtl);
|
|
end for;
|
|
for u12 : xwb_simple_uart
|
|
use entity work.xwb_simple_uart(rtl);
|
|
end for;
|
|
for u3 : xwb_tics
|
|
use entity work.xwb_tics(rtl);
|
|
end for;
|
|
for u5 : xwb_gpio_port
|
|
use entity work.xwb_gpio_port(rtl);
|
|
end for;
|
|
for u7 : xwb_i2c_master
|
|
use entity work.xwb_i2c_master(rtl);
|
|
end for;
|
|
for u8 : tri_state
|
|
use entity work.tri_state(structure);
|
|
end for;
|
|
for u10 : tri_state
|
|
use entity work.tri_state(structure);
|
|
end for;
|
|
for u14 : xwb_i2c_master
|
|
use entity work.xwb_i2c_master(rtl);
|
|
end for;
|
|
for u16 : tri_state
|
|
use entity work.tri_state(structure);
|
|
end for;
|
|
for u17 : tri_state
|
|
use entity work.tri_state(structure);
|
|
end for;
|
|
for u15 : xwb_date_rev_id
|
|
use entity work.xwb_date_rev_id(rtl);
|
|
end for;
|
|
for u18 : xwb_spi
|
|
use entity work.xwb_spi(rtl);
|
|
end for;
|
|
for u11 : xwb_tdc
|
|
use entity work.xwb_tdc(rtl);
|
|
end for;
|
|
for u19 : xwb_aes
|
|
use entity work.xwb_aes(rtl);
|
|
end for;
|
|
for u13 : DummySlave
|
|
use entity work.DummySlave(a0);
|
|
end for;
|
|
for u20 : DummySlave
|
|
use entity work.DummySlave(a0);
|
|
end for;
|
|
for u21 : DummySlave
|
|
use entity work.DummySlave(a0);
|
|
end for;
|
|
for u22 : DummySlave
|
|
use entity work.DummySlave(a0);
|
|
end for;
|
|
for u23 : DummySlave
|
|
use entity work.DummySlave(a0);
|
|
end for;
|
|
for u24 : DummySlave
|
|
use entity work.DummySlave(a0);
|
|
end for;
|
|
for u25 : DummySlave
|
|
use entity work.DummySlave(a0);
|
|
end for;
|
|
end for;
|
|
end for;
|
|
for u1 : cmp_sys_clk_pll
|
|
use entity work.cmp_sys_clk_pll(xilinx);
|
|
end for;
|
|
for u2 : dummy_aes
|
|
use entity work.dummy_aes(rtl);
|
|
end for;
|
|
for u4 : dummy_tdc
|
|
use entity work.dummy_tdc(rtl);
|
|
end for;
|
|
for u6 : MetaStabelizer
|
|
use entity work.MetaStabelizer(rtl);
|
|
for rtl
|
|
for u0 : Reg1NoRst
|
|
use entity work.Reg1NoRst(rtl);
|
|
end for;
|
|
for u1 : Reg1NoRst
|
|
use entity work.Reg1NoRst(rtl);
|
|
end for;
|
|
end for;
|
|
end for;
|
|
for u8 : MetaStabelizer
|
|
use entity work.MetaStabelizer(rtl);
|
|
for rtl
|
|
for u0 : Reg1NoRst
|
|
use entity work.Reg1NoRst(rtl);
|
|
end for;
|
|
for u1 : Reg1NoRst
|
|
use entity work.Reg1NoRst(rtl);
|
|
end for;
|
|
end for;
|
|
end for;
|
|
for u9 : low
|
|
use entity work.low(structure);
|
|
end for;
|
|
end for;
|
|
end for;
|
|
for u4 : pullup1
|
|
use entity work.pullup1(structure);
|
|
end for;
|
|
for u5 : pullup1
|
|
use entity work.pullup1(structure);
|
|
end for;
|
|
for u6 : pullup1
|
|
use entity work.pullup1(structure);
|
|
end for;
|
|
end for;
|
|
end configuration Functional;
|
|
|