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456 lines
21 KiB
Plaintext
456 lines
21 KiB
Plaintext
Started implementation of fpga on ma 07-04-2014 at 15:46:46,38
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ngdbuild ...
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Command Line: c:\Xilinx\14.5\ISE_DS\ISE\bin\nt64\unwrapped\ngdbuild.exe
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-intstyle xflow -dd . -nt timestamp -uc fpga.ucf -p xc7k325t-ffg900-2 fpga.edf
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FPGA.ngd
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Executing edif2ngd -quiet "fpga.edf" "fpga.ngo"
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Release 14.5 - edif2ngd P.58f (nt64)
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Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
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Reading NGO file
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"p:/App/KM3Net/CLB/CLBv2/SVN_Valencia/CLBv2_peter/fw/TestDesigns/Knight_Rider/sy
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n/work/fpga.ngo" ...
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Gathering constraint information from source properties...
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Done.
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Annotating constraints to design from ucf file "fpga.ucf" ...
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Resolving constraint associations...
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Checking Constraint Associations...
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Done...
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Checking expanded design ...
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Partition Implementation Status
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-------------------------------
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No Partitions were found in this design.
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-------------------------------
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NGDBUILD Design Results Summary:
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Number of errors: 0
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Number of warnings: 0
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Writing NGD file "FPGA.ngd" ...
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Total REAL time to NGDBUILD completion: 11 sec
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Total CPU time to NGDBUILD completion: 5 sec
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Writing NGDBUILD log file "FPGA.bld"...
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NGDBUILD done.
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map ...
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Using target part "7k325tffg900-2".
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WARNING:Map:304 - The -global_opt option can't be used for the targeted device
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family. Map will continue processing using the standard map flow and ignore
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the -global_opt option.
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vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv
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INFO:Security:50 - The XILINXD_LICENSE_FILE environment variable is set to
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'@eems.nikhef.nl'.
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INFO:Security:52 - The LM_LICENSE_FILE environment variable is set to
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'@eems.nikhef.nl;@adige.nikhef.nl;tardes.nikhef.nl'.
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INFO:Security:56 - Part 'xc7k325t' is not a WebPack part.
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WARNING:Security:43 - No license file was found in the standard Xilinx license
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directory.
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WARNING:Security:44 - Since no license file was found,
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please run the Xilinx License Configuration Manager
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(xlcm or "Manage Xilinx Licenses")
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to assist in obtaining a license.
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WARNING:Security:42 - Your software subscription period has lapsed. Your current
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version of Xilinx tools will continue to function, but you no longer qualify for
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Xilinx software updates or new releases.
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----------------------------------------------------------------------
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Mapping design into LUTs...
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Running directed packing...
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Running delay-based LUT packing...
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Updating timing models...
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INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
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(.mrp).
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Running timing-driven placement...
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Total REAL time at the beginning of Placer: 22 secs
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Total CPU time at the beginning of Placer: 21 secs
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Phase 1.1 Initial Placement Analysis
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Phase 1.1 Initial Placement Analysis (Checksum:2cfbb980) REAL time: 27 secs
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Phase 2.7 Design Feasibility Check
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WARNING:Place:838 - An IO Bus with more than one IO standard is found.
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Components associated with this bus are as follows:
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Comp: LED(0) IOSTANDARD = LVCMOS15
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Comp: LED(1) IOSTANDARD = LVCMOS15
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Comp: LED(2) IOSTANDARD = LVCMOS15
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Comp: LED(3) IOSTANDARD = LVCMOS15
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Comp: LED(4) IOSTANDARD = LVCMOS25
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Comp: LED(5) IOSTANDARD = LVCMOS25
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Phase 2.7 Design Feasibility Check (Checksum:2cfbb980) REAL time: 27 secs
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Phase 3.31 Local Placement Optimization
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Phase 3.31 Local Placement Optimization (Checksum:2cfbb980) REAL time: 27 secs
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Phase 4.2 Initial Placement for Architecture Specific Features
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Phase 4.2 Initial Placement for Architecture Specific Features
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(Checksum:2cfbb980) REAL time: 29 secs
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Phase 5.30 Global Clock Region Assignment
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Phase 5.30 Global Clock Region Assignment (Checksum:2cfbb980) REAL time: 29 secs
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Phase 6.3 Local Placement Optimization
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Phase 6.3 Local Placement Optimization (Checksum:2cfbb980) REAL time: 30 secs
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Phase 7.5 Local Placement Optimization
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Phase 7.5 Local Placement Optimization (Checksum:2cfbb980) REAL time: 30 secs
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Phase 8.8 Global Placement
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.................................
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.....................................
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.....................................
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Phase 8.8 Global Placement (Checksum:7651e164) REAL time: 31 secs
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Phase 9.5 Local Placement Optimization
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Phase 9.5 Local Placement Optimization (Checksum:7651e164) REAL time: 31 secs
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Phase 10.18 Placement Optimization
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Phase 10.18 Placement Optimization (Checksum:6fa873c8) REAL time: 31 secs
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Phase 11.5 Local Placement Optimization
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Phase 11.5 Local Placement Optimization (Checksum:6fa873c8) REAL time: 31 secs
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Phase 12.34 Placement Validation
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Phase 12.34 Placement Validation (Checksum:6fa873c8) REAL time: 32 secs
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Total REAL time to Placer completion: 32 secs
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Total CPU time to Placer completion: 30 secs
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Running post-placement packing...
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Writing output files...
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Design Summary:
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Number of errors: 0
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Number of warnings: 2
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Slice Logic Utilization:
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Number of Slice Registers: 35 out of 407,600 1%
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Number used as Flip Flops: 35
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Number used as Latches: 0
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Number used as Latch-thrus: 0
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Number used as AND/OR logics: 0
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Number of Slice LUTs: 34 out of 203,800 1%
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Number used as logic: 33 out of 203,800 1%
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Number using O6 output only: 10
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Number using O5 output only: 23
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Number using O5 and O6: 0
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Number used as ROM: 0
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Number used as Memory: 0 out of 64,000 0%
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Number used exclusively as route-thrus: 1
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Number with same-slice register load: 0
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Number with same-slice carry load: 1
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Number with other load: 0
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Slice Logic Distribution:
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Number of occupied Slices: 9 out of 50,950 1%
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Number of LUT Flip Flop pairs used: 34
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Number with an unused Flip Flop: 0 out of 34 0%
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Number with an unused LUT: 0 out of 34 0%
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Number of fully used LUT-FF pairs: 34 out of 34 100%
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Number of unique control sets: 1
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Number of slice register sites lost
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to control set restrictions: 5 out of 407,600 1%
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A LUT Flip Flop pair for this architecture represents one LUT paired with
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one Flip Flop within a slice. A control set is a unique combination of
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clock, reset, set, and enable signals for a registered element.
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The Slice Logic Distribution report is not meaningful if the design is
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over-mapped for a non-slice resource or if Placement fails.
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OVERMAPPING of BRAM resources should be ignored if the design is
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over-mapped for a non-BRAM resource or if placement fails.
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IO Utilization:
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Number of bonded IOBs: 6 out of 500 1%
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Number of LOCed IOBs: 6 out of 6 100%
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Number of bonded IPADs: 2
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Number of LOCed IPADs: 2 out of 2 100%
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Specific Feature Utilization:
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Number of RAMB36E1/FIFO36E1s: 0 out of 445 0%
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Number of RAMB18E1/FIFO18E1s: 0 out of 890 0%
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Number of BUFG/BUFGCTRLs: 0 out of 32 0%
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Number of IDELAYE2/IDELAYE2_FINEDELAYs: 0 out of 500 0%
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Number of ILOGICE2/ILOGICE3/ISERDESE2s: 0 out of 500 0%
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Number of ODELAYE2/ODELAYE2_FINEDELAYs: 0 out of 150 0%
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Number of OLOGICE2/OLOGICE3/OSERDESE2s: 0 out of 500 0%
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Number of PHASER_IN/PHASER_IN_PHYs: 0 out of 40 0%
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Number of PHASER_OUT/PHASER_OUT_PHYs: 0 out of 40 0%
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Number of BSCANs: 0 out of 4 0%
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Number of BUFHCEs: 0 out of 168 0%
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Number of BUFRs: 0 out of 40 0%
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Number of CAPTUREs: 0 out of 1 0%
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Number of DNA_PORTs: 0 out of 1 0%
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Number of DSP48E1s: 0 out of 840 0%
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Number of EFUSE_USRs: 0 out of 1 0%
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Number of FRAME_ECCs: 0 out of 1 0%
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Number of GTXE2_CHANNELs: 0 out of 16 0%
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Number of GTXE2_COMMONs: 0 out of 4 0%
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Number of IBUFDS_GTE2s: 1 out of 8 12%
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Number of ICAPs: 0 out of 2 0%
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Number of IDELAYCTRLs: 0 out of 10 0%
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Number of IN_FIFOs: 0 out of 40 0%
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Number of MMCME2_ADVs: 0 out of 10 0%
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Number of OUT_FIFOs: 0 out of 40 0%
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Number of PCIE_2_1s: 0 out of 1 0%
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Number of PHASER_REFs: 0 out of 10 0%
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Number of PHY_CONTROLs: 0 out of 10 0%
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Number of PLLE2_ADVs: 0 out of 10 0%
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Number of STARTUPs: 0 out of 1 0%
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Number of XADCs: 0 out of 1 0%
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Average Fanout of Non-Clock Nets: 2.33
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Peak Memory Usage: 1102 MB
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Total REAL time to MAP completion: 33 secs
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Total CPU time to MAP completion: 31 secs
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Mapping completed.
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See MAP report file "fpga_map.mrp" for details.
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par ...
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Constraints file: fpga.pcf.
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Loading device for application Rf_Device from file '7k325t.nph' in environment c:\Xilinx\14.5\ISE_DS\ISE\.
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"FPGA" is an NCD, version 3.2, device xc7k325t, package ffg900, speed -2
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vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv
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INFO:Security:50 - The XILINXD_LICENSE_FILE environment variable is set to '@eems.nikhef.nl'.
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INFO:Security:52 - The LM_LICENSE_FILE environment variable is set to
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'@eems.nikhef.nl;@adige.nikhef.nl;tardes.nikhef.nl'.
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INFO:Security:56 - Part 'xc7k325t' is not a WebPack part.
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WARNING:Security:43 - No license file was found in the standard Xilinx license directory.
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WARNING:Security:44 - Since no license file was found,
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please run the Xilinx License Configuration Manager
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(xlcm or "Manage Xilinx Licenses")
|
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to assist in obtaining a license.
|
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WARNING:Security:42 - Your software subscription period has lapsed. Your current version of Xilinx tools will continue
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to function, but you no longer qualify for Xilinx software updates or new releases.
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----------------------------------------------------------------------
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Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)
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Initializing voltage to 0.970 Volts. (default - Range: 0.970 to 1.030 Volts)
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Device speed data version: "PRODUCTION 1.09 2013-03-26".
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Device Utilization Summary:
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Slice Logic Utilization:
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Number of Slice Registers: 35 out of 407,600 1%
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Number used as Flip Flops: 35
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Number used as Latches: 0
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Number used as Latch-thrus: 0
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Number used as AND/OR logics: 0
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Number of Slice LUTs: 34 out of 203,800 1%
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Number used as logic: 33 out of 203,800 1%
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Number using O6 output only: 10
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Number using O5 output only: 23
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Number using O5 and O6: 0
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Number used as ROM: 0
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Number used as Memory: 0 out of 64,000 0%
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Number used exclusively as route-thrus: 1
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Number with same-slice register load: 0
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Number with same-slice carry load: 1
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Number with other load: 0
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Slice Logic Distribution:
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Number of occupied Slices: 9 out of 50,950 1%
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Number of LUT Flip Flop pairs used: 34
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Number with an unused Flip Flop: 0 out of 34 0%
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Number with an unused LUT: 0 out of 34 0%
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Number of fully used LUT-FF pairs: 34 out of 34 100%
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Number of slice register sites lost
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to control set restrictions: 0 out of 407,600 0%
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A LUT Flip Flop pair for this architecture represents one LUT paired with
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one Flip Flop within a slice. A control set is a unique combination of
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clock, reset, set, and enable signals for a registered element.
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The Slice Logic Distribution report is not meaningful if the design is
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over-mapped for a non-slice resource or if Placement fails.
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OVERMAPPING of BRAM resources should be ignored if the design is
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over-mapped for a non-BRAM resource or if placement fails.
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IO Utilization:
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Number of bonded IOBs: 6 out of 500 1%
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Number of LOCed IOBs: 6 out of 6 100%
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Number of bonded IPADs: 2
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Number of LOCed IPADs: 2 out of 2 100%
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Specific Feature Utilization:
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Number of RAMB36E1/FIFO36E1s: 0 out of 445 0%
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Number of RAMB18E1/FIFO18E1s: 0 out of 890 0%
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Number of BUFG/BUFGCTRLs: 0 out of 32 0%
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Number of IDELAYE2/IDELAYE2_FINEDELAYs: 0 out of 500 0%
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Number of ILOGICE2/ILOGICE3/ISERDESE2s: 0 out of 500 0%
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Number of ODELAYE2/ODELAYE2_FINEDELAYs: 0 out of 150 0%
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Number of OLOGICE2/OLOGICE3/OSERDESE2s: 0 out of 500 0%
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Number of PHASER_IN/PHASER_IN_PHYs: 0 out of 40 0%
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Number of PHASER_OUT/PHASER_OUT_PHYs: 0 out of 40 0%
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Number of BSCANs: 0 out of 4 0%
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Number of BUFHCEs: 0 out of 168 0%
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Number of BUFRs: 0 out of 40 0%
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Number of CAPTUREs: 0 out of 1 0%
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Number of DNA_PORTs: 0 out of 1 0%
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Number of DSP48E1s: 0 out of 840 0%
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Number of EFUSE_USRs: 0 out of 1 0%
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Number of FRAME_ECCs: 0 out of 1 0%
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Number of GTXE2_CHANNELs: 0 out of 16 0%
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Number of GTXE2_COMMONs: 0 out of 4 0%
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Number of IBUFDS_GTE2s: 1 out of 8 12%
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Number of ICAPs: 0 out of 2 0%
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Number of IDELAYCTRLs: 0 out of 10 0%
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Number of IN_FIFOs: 0 out of 40 0%
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Number of MMCME2_ADVs: 0 out of 10 0%
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Number of OUT_FIFOs: 0 out of 40 0%
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Number of PCIE_2_1s: 0 out of 1 0%
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Number of PHASER_REFs: 0 out of 10 0%
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Number of PHY_CONTROLs: 0 out of 10 0%
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Number of PLLE2_ADVs: 0 out of 10 0%
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Number of STARTUPs: 0 out of 1 0%
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Number of XADCs: 0 out of 1 0%
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Overall effort level (-ol): High
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Router effort level (-rl): High
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Starting initial Timing Analysis. REAL time: 17 secs
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Finished initial Timing Analysis. REAL time: 17 secs
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Starting Router
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Phase 1 : 129 unrouted; REAL time: 21 secs
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Phase 2 : 106 unrouted; REAL time: 21 secs
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Phase 3 : 29 unrouted; REAL time: 21 secs
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Phase 4 : 29 unrouted; (Setup:0, Hold:724, Component Switching Limit:0) REAL time: 31 secs
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Updating file: fpga.ncd with current fully routed design.
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Phase 5 : 0 unrouted; (Setup:0, Hold:626, Component Switching Limit:0) REAL time: 32 secs
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Phase 6 : 0 unrouted; (Setup:0, Hold:626, Component Switching Limit:0) REAL time: 32 secs
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Phase 7 : 0 unrouted; (Setup:0, Hold:626, Component Switching Limit:0) REAL time: 32 secs
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Phase 8 : 0 unrouted; (Setup:0, Hold:626, Component Switching Limit:0) REAL time: 32 secs
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Phase 9 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 32 secs
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Total REAL time to Router completion: 32 secs
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Total CPU time to Router completion: 31 secs
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Partition Implementation Status
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-------------------------------
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No Partitions were found in this design.
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-------------------------------
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Generating "PAR" statistics.
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**************************
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Generating Clock Report
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**************************
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+---------------------+--------------+------+------+------------+-------------+
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| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
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+---------------------+--------------+------+------+------------+-------------+
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| O0 | Local| | 9 | 0.345 | 1.701 |
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+---------------------+--------------+------+------+------------+-------------+
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* Net Skew is the difference between the minimum and maximum routing
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only delays for the net. Note this is different from Clock Skew which
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is reported in TRCE timing report. Clock Skew is the difference between
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the minimum and maximum path delays which includes logic delays.
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* The fanout is the number of component pins not the individual BEL loads,
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for example SLICE loads not FF loads.
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Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0)
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Number of Timing Constraints that were not applied: 1
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Asterisk (*) preceding a constraint indicates it was not met.
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This may be due to a setup or hold violation.
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----------------------------------------------------------------------------------------------------------
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Constraint | Check | Worst Case | Best Case | Timing | Timing
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| | Slack | Achievable | Errors | Score
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----------------------------------------------------------------------------------------------------------
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TS_SysClk_n = PERIOD TIMEGRP "SysClk_n" 8 | SETUP | 6.433ns| 1.567ns| 0| 0
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ns HIGH 50% | HOLD | 0.100ns| | 0| 0
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----------------------------------------------------------------------------------------------------------
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TS_SysClk_p = PERIOD TIMEGRP "SysClk_p" 8 | MINPERIOD | 6.592ns| 1.408ns| 0| 0
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ns HIGH 50% | | | | |
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----------------------------------------------------------------------------------------------------------
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All constraints were met.
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Generating Pad Report.
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All signals are completely routed.
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Total REAL time to PAR completion: 46 secs
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Total CPU time to PAR completion: 34 secs
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Peak Memory Usage: 938 MB
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Placer: Placement generated during map.
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Routing: Completed - No errors found.
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Timing: Completed - No errors found.
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Number of error messages: 0
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Number of warning messages: 0
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Number of info messages: 0
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Writing design to file fpga.ncd
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PAR done!
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trce ...
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Loading device for application Rf_Device from file '7k325t.nph' in environment
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c:\Xilinx\14.5\ISE_DS\ISE\.
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"FPGA" is an NCD, version 3.2, device xc7k325t, package ffg900, speed -2
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Analysis completed Mon Apr 07 15:48:38 2014
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--------------------------------------------------------------------------------
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Generating Report ...
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Number of warnings: 0
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Total time: 16 secs
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bitgen ...
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INFO:Bitgen:40 - Replacing "Allow" with "allow" for option "UnconstrainedPins".
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Most commonly, bitgen has determined and will use a specific value instead of
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the generic command-line value of "Auto". Alternately, this message appears
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if the same option is specified multiple times on the command-line. In this
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case, the option listed last will be used.
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INFO:Bitgen:40 - Replacing "Auto" with "NoWait" for option "Match_cycle". Most
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commonly, bitgen has determined and will use a specific value instead of the
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generic command-line value of "Auto". Alternately, this message appears if
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the same option is specified multiple times on the command-line. In this
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case, the option listed last will be used.
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INFO:WebTalk:4 -
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P:/App/KM3Net/CLB/CLBv2/SVN_Valencia/CLBv2_peter/fw/TestDesigns/Knight_Rider/syn
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