NoIndexTests/gitified_old_clb_svn
0
Fork 0
Files Issues Design Reviews Releases
Files
master
New Design Review gitified_old_clb_svn/fw/TestDesigns/LM32_Test/top/FPGA.vhd

602 lines
19 KiB
VHDL
Raw Permalink Blame History

--------------------------------------------------------------------------------
--
-- This VHDL file was generated by EASE/HDL 7.4 Revision 9 from HDL Works B.V.
--
-- Ease library : work
-- HDL library : work
-- Host name : SERING
-- User name : peterj
-- Time stamp : Tue Jun 18 09:50:40 2013
--
-- Designed by :
-- Company : HDL Works
-- Project info :
--
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Object : Entity work.DummySlave
-- Last modified : Tue Jan 15 14:25:05 2013.
--------------------------------------------------------------------------------
library ieee, work;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
use work.wishbone_pkg.all;
entity DummySlave is
port(
slave_i : out t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out);
end entity DummySlave;
--------------------------------------------------------------------------------
-- Object : Architecture work.DummySlave.a0
-- Last modified : Tue Jan 15 14:25:05 2013.
--------------------------------------------------------------------------------
architecture a0 of DummySlave is
begin
-- Slave input wishbone signals
slave_i.cyc <= '0';
slave_i.stb <= '0';
slave_i.adr <= (Others => '0');
slave_i.sel <= "0000";
slave_i.we <= '0';
slave_i.dat <= (Others => '0');
-- Slave output wishbone signals
slave_o.ack <= '0';
slave_o.err <= '0';
slave_o.rty <= '0';
slave_o.stall <= '0';
slave_o.int <= '0';
slave_o.dat <= (Others => '0');
end architecture a0 ; -- of DummySlave
--------------------------------------------------------------------------------
-- Object : Entity work.Dum_mnic
-- Last modified : Tue Jan 15 14:28:09 2013.
--------------------------------------------------------------------------------
library ieee, work;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
use work.genram_pkg.all;
use work.wishbone_pkg.all;
entity Dum_mnic is
generic(
g_dpram_size : integer := 20480);
port(
dpram_wbb_i : out t_wishbone_slave_in;
dpram_wbb_o : in t_wishbone_slave_out);
end entity Dum_mnic;
--------------------------------------------------------------------------------
-- Object : Architecture work.Dum_mnic.a0
-- Last modified : Tue Jan 15 14:28:09 2013.
--------------------------------------------------------------------------------
architecture a0 of Dum_mnic is
constant c_mnic_memsize_log2 : integer := f_log2_size(g_dpram_size);
begin
dpram_wbb_i.cyc <= '1';
dpram_wbb_i.stb <= '1';
dpram_wbb_i.adr(c_mnic_memsize_log2-1 downto 0) <= "000000000000000";
dpram_wbb_i.sel <= "1111";
dpram_wbb_i.we <= '0';
dpram_wbb_i.dat <= "00000000000000000000000000000000";
-- mnic_mem_data_i <= dpram_wbb_o.dat;
end architecture a0 ; -- of Dum_mnic
--------------------------------------------------------------------------------
-- Object : Entity work.Reg1NoRst
-- Last modified : Mon Jan 14 15:05:41 2013.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
entity Reg1NoRst is
port(
Clk : in std_logic;
D : in std_logic;
O : out std_logic := '0';
O_n : out std_logic);
end entity Reg1NoRst;
--------------------------------------------------------------------------------
-- Object : Architecture work.Reg1NoRst.rtl
-- Last modified : Mon Jan 14 15:05:41 2013.
--------------------------------------------------------------------------------
architecture rtl of Reg1NoRst is
begin
Process (Clk)
Begin
If Rising_Edge(Clk) Then
O <= D;
O_n <= Not D;
End If;
End Process;
end architecture rtl ; -- of Reg1NoRst
--------------------------------------------------------------------------------
-- Object : Entity work.MetaStabelizer
-- Last modified : Mon Jan 14 15:05:19 2013.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
entity MetaStabelizer is
port(
Clk : in std_logic;
D : in std_logic;
O : out std_logic;
O_n : out std_logic);
end entity MetaStabelizer;
--------------------------------------------------------------------------------
-- Object : Architecture work.MetaStabelizer.rtl
-- Last modified : Mon Jan 14 15:05:19 2013.
--------------------------------------------------------------------------------
architecture rtl of MetaStabelizer is
signal O_net : std_logic := '0';
component Reg1NoRst
port(
Clk : in std_logic;
D : in std_logic;
O : out std_logic := '0';
O_n : out std_logic);
end component Reg1NoRst;
begin
u0: Reg1NoRst
port map(
Clk => Clk,
D => D,
O => O_net,
O_n => open);
u1: Reg1NoRst
port map(
Clk => Clk,
D => O_net,
O => O,
O_n => O_n);
end architecture rtl ; -- of MetaStabelizer
--------------------------------------------------------------------------------
-- Object : Entity work.Counter
-- Last modified : Mon Nov 19 11:51:35 2012.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
entity Counter is
port(
Clk : in std_logic;
Q : out std_logic_vector(31 downto 0);
Rst : in std_logic);
end entity Counter;
--------------------------------------------------------------------------------
-- Object : Architecture work.Counter.rtl
-- Last modified : Mon Nov 19 11:51:35 2012.
--------------------------------------------------------------------------------
architecture rtl of Counter is
begin
Process (Clk, Rst)
Variable Count: Unsigned(31 downto 0) := (Others => '0');
Begin
If Rst = '1' Then
Count := (Others => '0');
ElsIf Rising_Edge(Clk) Then
Count := Count + 1;
End If;
Q <= Std_Logic_Vector (Count);
End Process;
end architecture rtl ; -- of Counter
--------------------------------------------------------------------------------
-- Object : Entity work.FPGA
-- Last modified : Tue Jan 15 14:41:42 2013.
--------------------------------------------------------------------------------
library ieee, work;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
use work.wishbone_pkg.all;
use work.endpoint_pkg.all;
use work.wrcore_pkg.all;
entity FPGA is
generic(
g_dpram_size : natural := 20480);
port(
Blink : out std_logic;
ClkI_n : in std_logic;
ClkI_p : in std_logic;
RST_I : in std_logic;
Spy2 : out std_logic;
Spy3 : out std_logic;
sRx : in std_logic;
sTx : out std_logic);
end entity FPGA;
--------------------------------------------------------------------------------
-- Object : Architecture work.FPGA.a0
-- Last modified : Tue Jan 15 14:41:42 2013.
--------------------------------------------------------------------------------
library UNISIM;
--use UNISIM.IBUFDS_GTE2;
--use UNISIM.BUFG;
use UNISIM.ALL;
architecture a0 of FPGA is
-----------------------------------------------------------------------------
--WB Secondary Crossbar
-----------------------------------------------------------------------------
constant c_secbar_layout : t_sdb_record_array(7 downto 0) :=
(0 => f_sdb_embed_device(c_xwr_mini_nic_sdb, x"00000000"),
1 => f_sdb_embed_device(c_xwr_endpoint_sdb, x"00000100"),
2 => f_sdb_embed_device(c_xwr_softpll_ng_sdb, x"00000200"),
3 => f_sdb_embed_device(c_xwr_pps_gen_sdb, x"00000300"),
4 => f_sdb_embed_device(c_wrc_periph0_sdb, x"00000400"), -- Syscon
5 => f_sdb_embed_device(c_wrc_periph1_sdb, x"00000500"), -- UART
6 => f_sdb_embed_device(c_wrc_periph2_sdb, x"00000600"), -- 1-Wire
7 => f_sdb_embed_device(c_wrc_periph2_sdb, x"00000700") -- aux WB bus
);
constant c_secbar_sdb_address : t_wishbone_address := x"00000800";
constant c_secbar_bridge_sdb : t_sdb_bridge :=
f_xwb_bridge_layout_sdb(true, c_secbar_layout, c_secbar_sdb_address);
-----------------------------------------------------------------------------
--WB intercon
-----------------------------------------------------------------------------
constant c_layout : t_sdb_record_array(1 downto 0) :=
(0 => f_sdb_embed_device(f_xwb_dpram(g_dpram_size), x"00000000"),
1 => f_sdb_embed_bridge(c_secbar_bridge_sdb, x"00020000"));
constant c_sdb_address : t_wishbone_address := x"00030000";
signal Net_0 : std_logic_vector(31 downto 0);
signal Clk : std_logic;
signal u5_O : std_logic;
signal cbar_slave_i : t_wishbone_slave_in_array(2 downto 0);
signal cbar_slave_o : t_wishbone_slave_out_array(2 downto 0);
signal cbar_master_i : t_wishbone_master_in_array(1 downto 0);
signal cbar_master_o : t_wishbone_master_out_array(1 downto 0);
signal slave2_o : t_wishbone_slave_out;
signal dpram_wbb_i : t_wishbone_slave_in;
signal Rst : std_logic;
signal Spy3_net : std_logic;
signal secbar_master_i : t_wishbone_master_in_array(7 downto 0);
signal secbar_master_o : t_wishbone_master_out_array(7 downto 0);
signal xwb_sdb_crossbar_slave_i : t_wishbone_slave_in_array(0 downto 0);
signal xwb_sdb_crossbar_slave_o : t_wishbone_slave_out_array(0 downto 0);
signal rst_n_i : std_logic;
component Counter
port(
Clk : in std_logic;
Q : out std_logic_vector(31 downto 0);
Rst : in std_logic);
end component Counter;
component MetaStabelizer
port(
Clk : in std_logic;
D : in std_logic;
O : out std_logic;
O_n : out std_logic);
end component MetaStabelizer;
component IBUFDS_GTE2
port(
CEB : in std_logic;
I : in std_logic;
IB : in std_logic;
O : out std_logic;
ODIV2 : out std_logic);
end component IBUFDS_GTE2;
component BUFG
port(
I : in std_logic;
O : out std_logic);
end component BUFG;
component Dum_mnic
generic(
g_dpram_size : integer := 20480);
port(
dpram_wbb_i : out t_wishbone_slave_in;
dpram_wbb_o : in t_wishbone_slave_out);
end component Dum_mnic;
component DummySlave
port(
slave_i : out t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out);
end component DummySlave;
component xwb_lm32
generic(
g_profile : string := "medium_icache_debug");
port(
clk_sys_i : in std_logic;
dwb_i : in t_wishbone_master_in;
dwb_o : out t_wishbone_master_out;
irq_i : in std_logic_vector(31 downto 0);
iwb_i : in t_wishbone_master_in;
iwb_o : out t_wishbone_master_out;
rst_n_i : in std_logic);
end component xwb_lm32;
component xwb_dpram
generic(
g_init_file : string := "";
g_must_have_init_file : boolean := true;
g_slave2_interface_mode : t_wishbone_interface_mode := PIPELINED;
g_slave2_granularity : t_wishbone_address_granularity := WORD;
g_size : natural := 16384;
g_init_value : t_xwb_dpram_init := c_xwb_dpram_init_nothing;
g_slave1_interface_mode : t_wishbone_interface_mode := PIPELINED;
g_slave1_granularity : t_wishbone_address_granularity := WORD);
port(
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
slave1_i : in t_wishbone_slave_in;
slave1_o : out t_wishbone_slave_out;
slave2_i : in t_wishbone_slave_in;
slave2_o : out t_wishbone_slave_out);
end component xwb_dpram;
component xwb_sdb_crossbar
generic(
g_num_masters : integer := 3;
g_registered : boolean := true;
g_layout : t_sdb_record_array;
g_num_slaves : integer := 2;
g_wraparound : boolean := true;
g_sdb_addr : t_wishbone_address := x"00000000");
port(
clk_sys_i : in std_logic;
master_i : in t_wishbone_master_in_array(g_num_slaves-1 downto 0);
master_o : out t_wishbone_master_out_array(g_num_slaves-1 downto 0);
rst_n_i : in std_logic;
slave_i : in t_wishbone_slave_in_array(g_num_masters-1 downto 0);
slave_o : out t_wishbone_slave_out_array(g_num_masters-1 downto 0));
end component xwb_sdb_crossbar;
component xwb_simple_uart
generic(
g_with_virtual_uart : boolean := False;
g_with_physical_uart : boolean := True;
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD);
port(
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
uart_rxd_i : in std_logic;
uart_txd_o : out std_logic);
end component xwb_simple_uart;
begin
--This Metastabelizer also synchronizes RST_I
--to the CLK_I clock domain. Such a synchronous
--reset may be necessary to avoid asynchronous
--signal changes on the wb_memory that could
--trigger false write actions...
--SGMIICLK_Q0_P (pin G8)
--SGMIICLK_Q0_N (pin G7)
--connect to 125 MHz Xtal on KC705
--cbar_slave(2) ought to be
--connected to the PCI-express brigde
--WB_CON
--WB_SECONDARY_CON
Blink <= Net_0(24);
Spy2 <= Net_0(24);
sTx <= Spy3_net;
Spy3 <= Spy3_net;
u3: Counter
port map(
Clk => Clk,
Q => Net_0,
Rst => Rst);
u7: MetaStabelizer
port map(
Clk => Clk,
D => RST_I,
O => Rst,
O_n => rst_n_i);
u5: IBUFDS_GTE2
port map(
CEB => '0',
I => ClkI_p,
IB => ClkI_n,
O => u5_O,
ODIV2 => open);
u8: BUFG
port map(
I => u5_O,
O => Clk);
u6: Dum_mnic
generic map(
g_dpram_size => g_dpram_size)
port map(
dpram_wbb_i => dpram_wbb_i,
dpram_wbb_o => slave2_o);
u2: DummySlave
port map(
slave_i => cbar_slave_i(2),
slave_o => cbar_slave_o(2));
u10: DummySlave
port map(
slave_i => open,
slave_o => secbar_master_i(0));
u11: DummySlave
port map(
slave_i => open,
slave_o => secbar_master_i(1));
u13: DummySlave
port map(
slave_i => open,
slave_o => secbar_master_i(2));
u14: DummySlave
port map(
slave_i => open,
slave_o => secbar_master_i(3));
u15: DummySlave
port map(
slave_i => open,
slave_o => secbar_master_i(4));
u16: DummySlave
port map(
slave_i => open,
slave_o => secbar_master_i(6));
u17: DummySlave
port map(
slave_i => open,
slave_o => secbar_master_i(7));
u0: xwb_lm32
generic map(
g_profile => "medium_icache_debug")
port map(
clk_sys_i => Clk,
dwb_i => cbar_slave_o(0),
dwb_o => cbar_slave_i(0),
irq_i => x"00000000",
iwb_i => cbar_slave_o(1),
iwb_o => cbar_slave_i(1),
rst_n_i => rst_n_i);
u4: xwb_dpram
generic map(
g_init_file => "lm32_memory.ldr",
g_must_have_init_file => true,
g_slave2_interface_mode => PIPELINED,
g_slave2_granularity => WORD,
g_size => g_dpram_size,
g_init_value => c_xwb_dpram_init_nothing,
g_slave1_interface_mode => PIPELINED,
g_slave1_granularity => BYTE)
port map(
clk_sys_i => Clk,
rst_n_i => rst_n_i,
slave1_i => cbar_master_o(0),
slave1_o => cbar_master_i(0),
slave2_i => dpram_wbb_i,
slave2_o => slave2_o);
u1: xwb_sdb_crossbar
generic map(
g_num_masters => 3,
g_registered => true,
g_layout => c_layout,
g_num_slaves => 2,
g_wraparound => true,
g_sdb_addr => c_sdb_address)
port map(
clk_sys_i => Clk,
master_i => cbar_master_i,
master_o => cbar_master_o,
rst_n_i => rst_n_i,
slave_i => cbar_slave_i,
slave_o => cbar_slave_o);
u9: xwb_sdb_crossbar
generic map(
g_num_masters => 1,
g_registered => true,
g_layout => c_secbar_layout,
g_num_slaves => 8,
g_wraparound => true,
g_sdb_addr => c_secbar_sdb_address)
port map(
clk_sys_i => Clk,
master_i => secbar_master_i,
master_o => secbar_master_o,
rst_n_i => rst_n_i,
slave_i => xwb_sdb_crossbar_slave_i,
slave_o => xwb_sdb_crossbar_slave_o);
u12: xwb_simple_uart
generic map(
g_with_virtual_uart => False,
g_with_physical_uart => True,
g_interface_mode => PIPELINED,
g_address_granularity => BYTE)
port map(
clk_sys_i => Clk,
rst_n_i => rst_n_i,
slave_i => secbar_master_o(5),
slave_o => secbar_master_i(5),
uart_rxd_i => sRx,
uart_txd_o => Spy3_net);
xwb_sdb_crossbar_slave_i(0) <= cbar_master_o(1);
cbar_master_i(1) <= xwb_sdb_crossbar_slave_o(0);
end architecture a0 ; -- of FPGA
Reference in New Issue View Git Blame Copy Permalink