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850 lines
25 KiB
VHDL
850 lines
25 KiB
VHDL
--------------------------------------------------------------------------------
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--
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-- This VHDL file was generated by EASE/HDL 7.4 Revision 9 from HDL Works B.V.
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--
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-- Ease library : work
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-- HDL library : work
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-- Host name : SERING
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-- User name : peterj
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-- Time stamp : Tue Jun 18 09:50:14 2013
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--
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-- Designed by :
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-- Company : HDL Works
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-- Project info :
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--
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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-- Object : Entity work.SYSCON
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-- Last modified : Fri Oct 19 17:26:59 2012.
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--------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.std_logic_unsigned.all;
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entity SYSCON is
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port(
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ClkI_n : out std_logic;
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ClkI_p : out std_logic;
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RST_I : out std_logic);
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end entity SYSCON;
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--------------------------------------------------------------------------------
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-- Object : Architecture work.SYSCON.rtl
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-- Last modified : Fri Oct 19 17:26:59 2012.
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--------------------------------------------------------------------------------
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architecture rtl of SYSCON is
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begin
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Process
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-- 200 MHz = 5 ns, 125 MHz = 8 ns, 100 MHz = 10 ns, 27 MHz = 37 ns
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Constant ClockPeriod: Time := 8 ns;
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Variable Clock: Std_Logic;
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-- RST_I is de-asserted after 5 CLK_I cycles
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Variable RstCount: Integer range 0 to 15 := 5;
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Begin
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If now = 0 ns Then
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Clock := '0';
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Else
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Clock := Not Clock;
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If clock = '0' and RstCount > 0 Then
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RstCount := RstCount - 1;
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End If;
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End If;
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ClkI_p <= Clock;
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ClkI_n <= Not Clock;
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If RstCount > 0 Then
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RST_I <= '1';
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Else
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RST_I <= '0';
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End If;
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Wait for ClockPeriod / 2;
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End Process;
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end architecture rtl ; -- of SYSCON
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--------------------------------------------------------------------------------
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-- Object : Entity work.DummySlave
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-- Last modified : Tue Jan 15 14:25:05 2013.
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--------------------------------------------------------------------------------
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library ieee, work;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.std_logic_unsigned.all;
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use work.wishbone_pkg.all;
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entity DummySlave is
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port(
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slave_i : out t_wishbone_slave_in;
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slave_o : out t_wishbone_slave_out);
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end entity DummySlave;
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--------------------------------------------------------------------------------
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-- Object : Architecture work.DummySlave.a0
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-- Last modified : Tue Jan 15 14:25:05 2013.
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--------------------------------------------------------------------------------
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architecture a0 of DummySlave is
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begin
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-- Slave input wishbone signals
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slave_i.cyc <= '0';
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slave_i.stb <= '0';
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slave_i.adr <= (Others => '0');
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slave_i.sel <= "0000";
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slave_i.we <= '0';
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slave_i.dat <= (Others => '0');
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-- Slave output wishbone signals
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slave_o.ack <= '0';
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slave_o.err <= '0';
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slave_o.rty <= '0';
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slave_o.stall <= '0';
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slave_o.int <= '0';
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slave_o.dat <= (Others => '0');
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end architecture a0 ; -- of DummySlave
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--------------------------------------------------------------------------------
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-- Object : Entity work.Dum_mnic
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-- Last modified : Tue Jan 15 14:28:09 2013.
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--------------------------------------------------------------------------------
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library ieee, work;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.std_logic_unsigned.all;
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use work.genram_pkg.all;
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use work.wishbone_pkg.all;
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entity Dum_mnic is
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generic(
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g_dpram_size : integer := 20480);
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port(
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dpram_wbb_i : out t_wishbone_slave_in;
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dpram_wbb_o : in t_wishbone_slave_out);
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end entity Dum_mnic;
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--------------------------------------------------------------------------------
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-- Object : Architecture work.Dum_mnic.a0
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-- Last modified : Tue Jan 15 14:28:09 2013.
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--------------------------------------------------------------------------------
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architecture a0 of Dum_mnic is
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constant c_mnic_memsize_log2 : integer := f_log2_size(g_dpram_size);
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begin
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dpram_wbb_i.cyc <= '1';
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dpram_wbb_i.stb <= '1';
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dpram_wbb_i.adr(c_mnic_memsize_log2-1 downto 0) <= "000000000000000";
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dpram_wbb_i.sel <= "1111";
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dpram_wbb_i.we <= '0';
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dpram_wbb_i.dat <= "00000000000000000000000000000000";
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-- mnic_mem_data_i <= dpram_wbb_o.dat;
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end architecture a0 ; -- of Dum_mnic
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--------------------------------------------------------------------------------
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-- Object : Entity work.Reg1NoRst
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-- Last modified : Mon Jan 14 15:05:41 2013.
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--------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.std_logic_unsigned.all;
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entity Reg1NoRst is
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port(
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Clk : in std_logic;
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D : in std_logic;
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O : out std_logic := '0';
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O_n : out std_logic);
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end entity Reg1NoRst;
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--------------------------------------------------------------------------------
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-- Object : Architecture work.Reg1NoRst.rtl
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-- Last modified : Mon Jan 14 15:05:41 2013.
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--------------------------------------------------------------------------------
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architecture rtl of Reg1NoRst is
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begin
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Process (Clk)
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Begin
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If Rising_Edge(Clk) Then
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O <= D;
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O_n <= Not D;
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End If;
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End Process;
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end architecture rtl ; -- of Reg1NoRst
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--------------------------------------------------------------------------------
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-- Object : Entity work.MetaStabelizer
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-- Last modified : Mon Jan 14 15:05:19 2013.
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--------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.std_logic_unsigned.all;
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entity MetaStabelizer is
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port(
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Clk : in std_logic;
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D : in std_logic;
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O : out std_logic;
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O_n : out std_logic);
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end entity MetaStabelizer;
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--------------------------------------------------------------------------------
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-- Object : Architecture work.MetaStabelizer.rtl
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-- Last modified : Mon Jan 14 15:05:19 2013.
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--------------------------------------------------------------------------------
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architecture rtl of MetaStabelizer is
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signal O_net : std_logic := '0';
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component Reg1NoRst
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port(
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Clk : in std_logic;
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D : in std_logic;
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O : out std_logic := '0';
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O_n : out std_logic);
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end component Reg1NoRst;
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begin
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u0: Reg1NoRst
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port map(
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Clk => Clk,
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D => D,
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O => O_net,
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O_n => open);
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u1: Reg1NoRst
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port map(
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Clk => Clk,
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D => O_net,
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O => O,
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O_n => O_n);
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end architecture rtl ; -- of MetaStabelizer
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--------------------------------------------------------------------------------
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-- Object : Entity work.Counter
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-- Last modified : Mon Nov 19 11:51:35 2012.
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--------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.std_logic_unsigned.all;
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entity Counter is
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port(
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Clk : in std_logic;
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Q : out std_logic_vector(31 downto 0);
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Rst : in std_logic);
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end entity Counter;
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--------------------------------------------------------------------------------
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-- Object : Architecture work.Counter.rtl
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-- Last modified : Mon Nov 19 11:51:35 2012.
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--------------------------------------------------------------------------------
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architecture rtl of Counter is
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begin
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Process (Clk, Rst)
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Variable Count: Unsigned(31 downto 0) := (Others => '0');
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Begin
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If Rst = '1' Then
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Count := (Others => '0');
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ElsIf Rising_Edge(Clk) Then
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Count := Count + 1;
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End If;
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Q <= Std_Logic_Vector (Count);
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End Process;
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end architecture rtl ; -- of Counter
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--------------------------------------------------------------------------------
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-- Object : Entity work.FPGA
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-- Last modified : Tue Jan 15 14:41:42 2013.
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--------------------------------------------------------------------------------
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library ieee, work;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.std_logic_unsigned.all;
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use work.wishbone_pkg.all;
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use work.endpoint_pkg.all;
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use work.wrcore_pkg.all;
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entity FPGA is
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generic(
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g_dpram_size : natural := 20480);
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port(
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Blink : out std_logic;
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ClkI_n : in std_logic;
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ClkI_p : in std_logic;
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RST_I : in std_logic;
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Spy2 : out std_logic;
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Spy3 : out std_logic;
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sRx : in std_logic;
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sTx : out std_logic);
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end entity FPGA;
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--------------------------------------------------------------------------------
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-- Object : Architecture work.FPGA.a0
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-- Last modified : Tue Jan 15 14:41:42 2013.
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--------------------------------------------------------------------------------
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library UNISIM;
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use UNISIM.IBUFDS_GTE2;
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use UNISIM.BUFG;
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architecture a0 of FPGA is
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-----------------------------------------------------------------------------
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--WB Secondary Crossbar
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-----------------------------------------------------------------------------
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constant c_secbar_layout : t_sdb_record_array(7 downto 0) :=
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(0 => f_sdb_embed_device(c_xwr_mini_nic_sdb, x"00000000"),
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1 => f_sdb_embed_device(c_xwr_endpoint_sdb, x"00000100"),
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2 => f_sdb_embed_device(c_xwr_softpll_ng_sdb, x"00000200"),
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3 => f_sdb_embed_device(c_xwr_pps_gen_sdb, x"00000300"),
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4 => f_sdb_embed_device(c_wrc_periph0_sdb, x"00000400"), -- Syscon
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5 => f_sdb_embed_device(c_wrc_periph1_sdb, x"00000500"), -- UART
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6 => f_sdb_embed_device(c_wrc_periph2_sdb, x"00000600"), -- 1-Wire
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7 => f_sdb_embed_device(c_wrc_periph2_sdb, x"00000700") -- aux WB bus
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);
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constant c_secbar_sdb_address : t_wishbone_address := x"00000800";
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constant c_secbar_bridge_sdb : t_sdb_bridge :=
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f_xwb_bridge_layout_sdb(true, c_secbar_layout, c_secbar_sdb_address);
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-----------------------------------------------------------------------------
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--WB intercon
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-----------------------------------------------------------------------------
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constant c_layout : t_sdb_record_array(1 downto 0) :=
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(0 => f_sdb_embed_device(f_xwb_dpram(g_dpram_size), x"00000000"),
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1 => f_sdb_embed_bridge(c_secbar_bridge_sdb, x"00020000"));
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constant c_sdb_address : t_wishbone_address := x"00030000";
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signal Net_0 : std_logic_vector(31 downto 0);
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signal Clk : std_logic;
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signal u5_O : std_logic;
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signal cbar_slave_i : t_wishbone_slave_in_array(2 downto 0);
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signal cbar_slave_o : t_wishbone_slave_out_array(2 downto 0);
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signal cbar_master_i : t_wishbone_master_in_array(1 downto 0);
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signal cbar_master_o : t_wishbone_master_out_array(1 downto 0);
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signal slave2_o : t_wishbone_slave_out;
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signal dpram_wbb_i : t_wishbone_slave_in;
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signal Rst : std_logic;
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signal Spy3_net : std_logic;
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signal secbar_master_i : t_wishbone_master_in_array(7 downto 0);
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signal secbar_master_o : t_wishbone_master_out_array(7 downto 0);
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signal xwb_sdb_crossbar_slave_i : t_wishbone_slave_in_array(0 downto 0);
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signal xwb_sdb_crossbar_slave_o : t_wishbone_slave_out_array(0 downto 0);
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signal rst_n_i : std_logic;
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component Counter
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port(
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Clk : in std_logic;
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Q : out std_logic_vector(31 downto 0);
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Rst : in std_logic);
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end component Counter;
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component MetaStabelizer
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port(
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Clk : in std_logic;
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D : in std_logic;
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O : out std_logic;
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O_n : out std_logic);
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end component MetaStabelizer;
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component IBUFDS_GTE2
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port(
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CEB : in std_logic;
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I : in std_logic;
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IB : in std_logic;
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O : out std_logic;
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ODIV2 : out std_logic);
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end component IBUFDS_GTE2;
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component BUFG
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port(
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I : in std_logic;
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O : out std_logic);
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end component BUFG;
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component Dum_mnic
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generic(
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g_dpram_size : integer := 20480);
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port(
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dpram_wbb_i : out t_wishbone_slave_in;
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dpram_wbb_o : in t_wishbone_slave_out);
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end component Dum_mnic;
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component DummySlave
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port(
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slave_i : out t_wishbone_slave_in;
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slave_o : out t_wishbone_slave_out);
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end component DummySlave;
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component xwb_lm32
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generic(
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g_profile : string := "medium_icache_debug");
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port(
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clk_sys_i : in std_logic;
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dwb_i : in t_wishbone_master_in;
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dwb_o : out t_wishbone_master_out;
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irq_i : in std_logic_vector(31 downto 0);
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iwb_i : in t_wishbone_master_in;
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iwb_o : out t_wishbone_master_out;
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rst_n_i : in std_logic);
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end component xwb_lm32;
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component xwb_dpram
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generic(
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g_init_file : string := "";
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g_must_have_init_file : boolean := true;
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g_slave2_interface_mode : t_wishbone_interface_mode := PIPELINED;
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g_slave2_granularity : t_wishbone_address_granularity := WORD;
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g_size : natural := 16384;
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g_init_value : t_xwb_dpram_init := c_xwb_dpram_init_nothing;
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g_slave1_interface_mode : t_wishbone_interface_mode := PIPELINED;
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g_slave1_granularity : t_wishbone_address_granularity := WORD);
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port(
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clk_sys_i : in std_logic;
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rst_n_i : in std_logic;
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slave1_i : in t_wishbone_slave_in;
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slave1_o : out t_wishbone_slave_out;
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slave2_i : in t_wishbone_slave_in;
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slave2_o : out t_wishbone_slave_out);
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end component xwb_dpram;
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component xwb_sdb_crossbar
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generic(
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g_num_masters : integer := 3;
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g_registered : boolean := true;
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g_layout : t_sdb_record_array;
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g_num_slaves : integer := 2;
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g_wraparound : boolean := true;
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g_sdb_addr : t_wishbone_address := x"00000000");
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port(
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clk_sys_i : in std_logic;
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master_i : in t_wishbone_master_in_array(g_num_slaves-1 downto 0);
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master_o : out t_wishbone_master_out_array(g_num_slaves-1 downto 0);
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rst_n_i : in std_logic;
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slave_i : in t_wishbone_slave_in_array(g_num_masters-1 downto 0);
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slave_o : out t_wishbone_slave_out_array(g_num_masters-1 downto 0));
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end component xwb_sdb_crossbar;
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component xwb_simple_uart
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generic(
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g_with_virtual_uart : boolean := False;
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g_with_physical_uart : boolean := True;
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g_interface_mode : t_wishbone_interface_mode := CLASSIC;
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g_address_granularity : t_wishbone_address_granularity := WORD);
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port(
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clk_sys_i : in std_logic;
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rst_n_i : in std_logic;
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slave_i : in t_wishbone_slave_in;
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slave_o : out t_wishbone_slave_out;
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uart_rxd_i : in std_logic;
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uart_txd_o : out std_logic);
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end component xwb_simple_uart;
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begin
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--This Metastabelizer also synchronizes RST_I
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--to the CLK_I clock domain. Such a synchronous
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--reset may be necessary to avoid asynchronous
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--signal changes on the wb_memory that could
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--trigger false write actions...
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--SGMIICLK_Q0_P (pin G8)
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--SGMIICLK_Q0_N (pin G7)
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--connect to 125 MHz Xtal on KC705
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--cbar_slave(2) ought to be
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--connected to the PCI-express brigde
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--WB_CON
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--WB_SECONDARY_CON
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Blink <= Net_0(24);
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Spy2 <= Net_0(24);
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sTx <= Spy3_net;
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Spy3 <= Spy3_net;
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u3: Counter
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port map(
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Clk => Clk,
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Q => Net_0,
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Rst => Rst);
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u7: MetaStabelizer
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port map(
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Clk => Clk,
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D => RST_I,
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O => Rst,
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O_n => rst_n_i);
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u5: IBUFDS_GTE2
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port map(
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CEB => '0',
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I => ClkI_p,
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IB => ClkI_n,
|
|
O => u5_O,
|
|
ODIV2 => open);
|
|
|
|
u8: BUFG
|
|
port map(
|
|
I => u5_O,
|
|
O => Clk);
|
|
|
|
u6: Dum_mnic
|
|
generic map(
|
|
g_dpram_size => g_dpram_size)
|
|
port map(
|
|
dpram_wbb_i => dpram_wbb_i,
|
|
dpram_wbb_o => slave2_o);
|
|
|
|
u2: DummySlave
|
|
port map(
|
|
slave_i => cbar_slave_i(2),
|
|
slave_o => cbar_slave_o(2));
|
|
|
|
u10: DummySlave
|
|
port map(
|
|
slave_i => open,
|
|
slave_o => secbar_master_i(0));
|
|
|
|
u11: DummySlave
|
|
port map(
|
|
slave_i => open,
|
|
slave_o => secbar_master_i(1));
|
|
|
|
u13: DummySlave
|
|
port map(
|
|
slave_i => open,
|
|
slave_o => secbar_master_i(2));
|
|
|
|
u14: DummySlave
|
|
port map(
|
|
slave_i => open,
|
|
slave_o => secbar_master_i(3));
|
|
|
|
u15: DummySlave
|
|
port map(
|
|
slave_i => open,
|
|
slave_o => secbar_master_i(4));
|
|
|
|
u16: DummySlave
|
|
port map(
|
|
slave_i => open,
|
|
slave_o => secbar_master_i(6));
|
|
|
|
u17: DummySlave
|
|
port map(
|
|
slave_i => open,
|
|
slave_o => secbar_master_i(7));
|
|
|
|
u0: xwb_lm32
|
|
generic map(
|
|
g_profile => "medium_icache_debug")
|
|
port map(
|
|
clk_sys_i => Clk,
|
|
dwb_i => cbar_slave_o(0),
|
|
dwb_o => cbar_slave_i(0),
|
|
irq_i => x"00000000",
|
|
iwb_i => cbar_slave_o(1),
|
|
iwb_o => cbar_slave_i(1),
|
|
rst_n_i => rst_n_i);
|
|
|
|
u4: xwb_dpram
|
|
generic map(
|
|
g_init_file => "lm32_memory.ldr",
|
|
g_must_have_init_file => true,
|
|
g_slave2_interface_mode => PIPELINED,
|
|
g_slave2_granularity => WORD,
|
|
g_size => g_dpram_size,
|
|
g_init_value => c_xwb_dpram_init_nothing,
|
|
g_slave1_interface_mode => PIPELINED,
|
|
g_slave1_granularity => BYTE)
|
|
port map(
|
|
clk_sys_i => Clk,
|
|
rst_n_i => rst_n_i,
|
|
slave1_i => cbar_master_o(0),
|
|
slave1_o => cbar_master_i(0),
|
|
slave2_i => dpram_wbb_i,
|
|
slave2_o => slave2_o);
|
|
|
|
u1: xwb_sdb_crossbar
|
|
generic map(
|
|
g_num_masters => 3,
|
|
g_registered => true,
|
|
g_layout => c_layout,
|
|
g_num_slaves => 2,
|
|
g_wraparound => true,
|
|
g_sdb_addr => c_sdb_address)
|
|
port map(
|
|
clk_sys_i => Clk,
|
|
master_i => cbar_master_i,
|
|
master_o => cbar_master_o,
|
|
rst_n_i => rst_n_i,
|
|
slave_i => cbar_slave_i,
|
|
slave_o => cbar_slave_o);
|
|
|
|
u9: xwb_sdb_crossbar
|
|
generic map(
|
|
g_num_masters => 1,
|
|
g_registered => true,
|
|
g_layout => c_secbar_layout,
|
|
g_num_slaves => 8,
|
|
g_wraparound => true,
|
|
g_sdb_addr => c_secbar_sdb_address)
|
|
port map(
|
|
clk_sys_i => Clk,
|
|
master_i => secbar_master_i,
|
|
master_o => secbar_master_o,
|
|
rst_n_i => rst_n_i,
|
|
slave_i => xwb_sdb_crossbar_slave_i,
|
|
slave_o => xwb_sdb_crossbar_slave_o);
|
|
|
|
u12: xwb_simple_uart
|
|
generic map(
|
|
g_with_virtual_uart => False,
|
|
g_with_physical_uart => True,
|
|
g_interface_mode => PIPELINED,
|
|
g_address_granularity => BYTE)
|
|
port map(
|
|
clk_sys_i => Clk,
|
|
rst_n_i => rst_n_i,
|
|
slave_i => secbar_master_o(5),
|
|
slave_o => secbar_master_i(5),
|
|
uart_rxd_i => sRx,
|
|
uart_txd_o => Spy3_net);
|
|
|
|
|
|
xwb_sdb_crossbar_slave_i(0) <= cbar_master_o(1);
|
|
cbar_master_i(1) <= xwb_sdb_crossbar_slave_o(0);
|
|
end architecture a0 ; -- of FPGA
|
|
|
|
--------------------------------------------------------------------------------
|
|
-- Object : Entity work.SystemTop
|
|
-- Last modified : Wed Apr 03 14:27:59 2013.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
|
|
library ieee;
|
|
use ieee.std_logic_1164.all;
|
|
use ieee.numeric_std.all;
|
|
use ieee.std_logic_unsigned.all;
|
|
|
|
entity SystemTop is
|
|
port(
|
|
Blink : out std_logic;
|
|
RST_I : in std_logic;
|
|
Spy2 : out std_logic;
|
|
Spy3 : out std_logic;
|
|
TCK : in std_logic;
|
|
TDI : in std_logic;
|
|
TDO : out std_logic;
|
|
TMS : in std_logic;
|
|
sRx : in std_logic;
|
|
sTX : out std_logic);
|
|
end entity SystemTop;
|
|
|
|
--------------------------------------------------------------------------------
|
|
-- Object : Architecture work.SystemTop.a0
|
|
-- Last modified : Wed Apr 03 14:27:59 2013.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
library UNISIM;
|
|
use UNISIM.JTAG_SIME2_SUBMOD;
|
|
|
|
architecture a0 of SystemTop is
|
|
|
|
signal ClkI_p : std_logic;
|
|
signal ClkI_n : std_logic;
|
|
|
|
component FPGA
|
|
generic(
|
|
g_dpram_size : natural := 20480);
|
|
port(
|
|
Blink : out std_logic;
|
|
ClkI_n : in std_logic;
|
|
ClkI_p : in std_logic;
|
|
RST_I : in std_logic;
|
|
Spy2 : out std_logic;
|
|
Spy3 : out std_logic;
|
|
sRx : in std_logic;
|
|
sTx : out std_logic);
|
|
end component FPGA;
|
|
|
|
component SYSCON
|
|
port(
|
|
ClkI_n : out std_logic;
|
|
ClkI_p : out std_logic;
|
|
RST_I : out std_logic);
|
|
end component SYSCON;
|
|
|
|
component JTAG_SIME2_SUBMOD
|
|
generic(
|
|
PART_NAME : string;
|
|
IRLength : integer := 0);
|
|
port(
|
|
TCK : in std_logic;
|
|
TDI : in std_logic;
|
|
TDO : out std_logic;
|
|
TMS : in std_logic);
|
|
end component JTAG_SIME2_SUBMOD;
|
|
|
|
begin
|
|
u0: FPGA
|
|
generic map(
|
|
g_dpram_size => 20480)
|
|
port map(
|
|
Blink => Blink,
|
|
ClkI_n => ClkI_n,
|
|
ClkI_p => ClkI_p,
|
|
RST_I => RST_I,
|
|
Spy2 => Spy2,
|
|
Spy3 => Spy3,
|
|
sRx => sRx,
|
|
sTx => sTX);
|
|
|
|
u1: SYSCON
|
|
port map(
|
|
ClkI_n => ClkI_n,
|
|
ClkI_p => ClkI_p,
|
|
RST_I => open);
|
|
|
|
u3: JTAG_SIME2_SUBMOD
|
|
generic map(
|
|
PART_NAME => "7k325t",
|
|
IRLength => 6)
|
|
port map(
|
|
TCK => TCK,
|
|
TDI => TDI,
|
|
TDO => TDO,
|
|
TMS => TMS);
|
|
|
|
end architecture a0 ; -- of SystemTop
|
|
|
|
--------------------------------------------------------------------------------
|
|
-- Object : Configuration work.SystemTop.Functional
|
|
-- Last modified : Wed Apr 03 14:27:59 2013.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
library work, UNISIM;
|
|
|
|
|
|
configuration Functional of SystemTop is
|
|
for a0
|
|
for u0 : FPGA
|
|
use entity work.FPGA(a0);
|
|
for a0
|
|
for u3 : Counter
|
|
use entity work.Counter(rtl);
|
|
end for;
|
|
for u7 : MetaStabelizer
|
|
use entity work.MetaStabelizer(rtl);
|
|
for rtl
|
|
for u0 : Reg1NoRst
|
|
use entity work.Reg1NoRst(rtl);
|
|
end for;
|
|
for u1 : Reg1NoRst
|
|
use entity work.Reg1NoRst(rtl);
|
|
end for;
|
|
end for;
|
|
end for;
|
|
for u5 : IBUFDS_GTE2
|
|
use entity UNISIM.IBUFDS_GTE2(IBUFDS_GTE2_V);
|
|
end for;
|
|
for u8 : BUFG
|
|
use entity UNISIM.BUFG(BUFG_V);
|
|
end for;
|
|
for u6 : Dum_mnic
|
|
use entity work.Dum_mnic(a0);
|
|
end for;
|
|
for u2 : DummySlave
|
|
use entity work.DummySlave(a0);
|
|
end for;
|
|
for u10 : DummySlave
|
|
use entity work.DummySlave(a0);
|
|
end for;
|
|
for u11 : DummySlave
|
|
use entity work.DummySlave(a0);
|
|
end for;
|
|
for u13 : DummySlave
|
|
use entity work.DummySlave(a0);
|
|
end for;
|
|
for u14 : DummySlave
|
|
use entity work.DummySlave(a0);
|
|
end for;
|
|
for u15 : DummySlave
|
|
use entity work.DummySlave(a0);
|
|
end for;
|
|
for u16 : DummySlave
|
|
use entity work.DummySlave(a0);
|
|
end for;
|
|
for u17 : DummySlave
|
|
use entity work.DummySlave(a0);
|
|
end for;
|
|
for u0 : xwb_lm32
|
|
use entity work.xwb_lm32(rtl);
|
|
end for;
|
|
for u4 : xwb_dpram
|
|
use entity work.xwb_dpram(struct);
|
|
end for;
|
|
for u1 : xwb_sdb_crossbar
|
|
use entity work.xwb_sdb_crossbar(rtl);
|
|
end for;
|
|
for u9 : xwb_sdb_crossbar
|
|
use entity work.xwb_sdb_crossbar(rtl);
|
|
end for;
|
|
for u12 : xwb_simple_uart
|
|
use entity work.xwb_simple_uart(rtl);
|
|
end for;
|
|
end for;
|
|
end for;
|
|
for u1 : SYSCON
|
|
use entity work.SYSCON(rtl);
|
|
end for;
|
|
for u3 : JTAG_SIME2_SUBMOD
|
|
use entity UNISIM.JTAG_SIME2_SUBMOD(JTAG_SIME2_SUBMOD_V);
|
|
end for;
|
|
end for;
|
|
end configuration Functional;
|
|
|