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153 lines
4.5 KiB
VHDL
153 lines
4.5 KiB
VHDL
-------------------------------------------------------------------------------
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-- Title : WhiteRabbit PTP Core tics
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-- Project : WhiteRabbit
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-------------------------------------------------------------------------------
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-- File : wb_tics.vhd
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-- Author : Grzegorz Daniluk
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-- Company : Elproma
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-- Created : 2011-04-03
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-- Last update: 2011-10-04
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-- Platform : FPGA-generics
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-- Standard : VHDL'93
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-------------------------------------------------------------------------------
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-- Description:
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-- WB_TICS is a simple counter with wishbone interface. Each step of a counter
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-- takes 1 usec. It is used by ptp-noposix as a replace of gettimeofday()
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-- function.
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-------------------------------------------------------------------------------
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-- Copyright (c) 2011 Grzegorz Daniluk
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-------------------------------------------------------------------------------
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-- Revisions :
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-- Date Version Author Description
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-- 2011-04-03 1.0 greg.d Created
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-- 2011-10-04 1.1 twlostow added wishbone adapter
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.wishbone_pkg.all;
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entity wb_watchdog is
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generic (
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g_interface_mode : t_wishbone_interface_mode := CLASSIC;
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g_address_granularity : t_wishbone_address_granularity := WORD;
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g_period : integer);
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port(
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rst_n_i : in std_logic;
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clk_sys_i : in std_logic;
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wb_adr_i : in std_logic_vector(3 downto 0);
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wb_dat_i : in std_logic_vector(c_wishbone_data_width-1 downto 0);
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wb_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0);
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wb_cyc_i : in std_logic;
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wb_sel_i : in std_logic_vector(c_wishbone_data_width/8-1 downto 0);
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wb_stb_i : in std_logic;
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wb_we_i : in std_logic;
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wb_ack_o : out std_logic;
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wb_stall_o: out std_logic
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);
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end wb_tics;
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architecture behaviour of wb_watchdog is
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constant c_TICS_REG : std_logic_vector(1 downto 0) := "00";
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signal cntr_div : unsigned(23 downto 0);
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signal cntr_tics : unsigned(31 downto 0);
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signal cntr_overflow : std_logic;
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signal wb_in : t_wishbone_slave_in;
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signal wb_out : t_wishbone_slave_out;
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signal resized_addr : std_logic_vector(c_wishbone_address_width-1 downto 0);
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begin
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resized_addr(3 downto 0) <= wb_adr_i;
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resized_addr(c_wishbone_address_width-1 downto 4) <= (others => '0');
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U_Adapter : wb_slave_adapter
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generic map (
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g_master_use_struct => true,
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g_master_mode => CLASSIC,
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g_master_granularity => WORD,
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g_slave_use_struct => false,
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g_slave_mode => g_interface_mode,
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g_slave_granularity => g_address_granularity)
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port map (
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clk_sys_i => clk_sys_i,
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rst_n_i => rst_n_i,
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master_i => wb_out,
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master_o => wb_in,
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sl_adr_i => resized_addr,
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sl_dat_i => wb_dat_i,
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sl_sel_i => wb_sel_i,
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sl_cyc_i => wb_cyc_i,
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sl_stb_i => wb_stb_i,
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sl_we_i => wb_we_i,
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sl_dat_o => wb_dat_o,
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sl_ack_o => wb_ack_o,
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sl_stall_o => wb_stall_o);
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process(clk_sys_i)
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begin
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if rising_edge(clk_sys_i) then
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if(rst_n_i = '0') then
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cntr_div <= (others => '0');
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cntr_overflow <= '0';
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else
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if(cntr_div = g_period-1) then
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cntr_div <= (others => '0');
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cntr_overflow <= '1';
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else
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cntr_div <= cntr_div + 1;
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cntr_overflow <= '0';
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end if;
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end if;
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end if;
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end process;
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--usec counter
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process(clk_sys_i)
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begin
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if(rising_edge(clk_sys_i)) then
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if(rst_n_i = '0') then
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cntr_tics <= (others => '0');
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elsif(cntr_overflow = '1') then
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cntr_tics <= cntr_tics + 1;
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end if;
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end if;
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end process;
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--Wishbone interface
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process(clk_sys_i)
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begin
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if rising_edge(clk_sys_i) then
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if(rst_n_i = '0') then
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wb_out.ack <= '0';
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wb_out.dat <= (others => '0');
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else
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if(wb_in.stb = '1' and wb_in.cyc = '1') then
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if(wb_in.we = '0') then
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case wb_in.adr(1 downto 0) is
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when c_TICS_REG =>
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wb_out.dat <= std_logic_vector(cntr_tics);
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when others =>
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wb_out.dat <= (others => '0');
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end case;
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end if;
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wb_out.ack <= '1';
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else
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wb_out.dat <= (others => '0');
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wb_out.ack <= '0';
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end if;
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end if;
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end if;
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end process;
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end behaviour;
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