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74 lines
2.0 KiB
VHDL
74 lines
2.0 KiB
VHDL
-- todo: configurable interrupt, output compare, PWM?
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library ieee;
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use ieee.std_logic_1164.all;
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use work.wishbone_pkg.all;
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entity xwb_watchdog is
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generic(
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g_interface_mode : t_wishbone_interface_mode := CLASSIC;
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g_address_granularity : t_wishbone_address_granularity := WORD;
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g_period : integer
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);
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port(
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clk_sys_i : in std_logic;
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rst_n_i : in std_logic;
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-- Wishbone
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slave_i : in t_wishbone_slave_in;
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slave_o : out t_wishbone_slave_out;
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desc_o : out t_wishbone_device_descriptor
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);
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end xwb_tics;
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architecture rtl of xwb_watchdog is
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component wb_watchdog
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generic (
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g_interface_mode : t_wishbone_interface_mode := CLASSIC;
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g_address_granularity : t_wishbone_address_granularity := WORD;
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g_period : integer);
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port (
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rst_n_i : in std_logic;
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clk_sys_i : in std_logic;
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wb_adr_i : in std_logic_vector(3 downto 0);
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wb_dat_i : in std_logic_vector(c_wishbone_data_width-1 downto 0);
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wb_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0);
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wb_cyc_i : in std_logic;
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wb_sel_i : in std_logic_vector(c_wishbone_data_width/8-1 downto 0);
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wb_stb_i : in std_logic;
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wb_we_i : in std_logic;
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wb_ack_o : out std_logic;
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wb_stall_o : out std_logic);
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end component;
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begin
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U_Tics : wb_watchdog
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generic map (
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g_interface_mode => g_interface_mode,
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g_address_granularity => g_address_granularity,
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g_period => g_period)
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port map (
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rst_n_i => rst_n_i,
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clk_sys_i => clk_sys_i,
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wb_adr_i => slave_i.adr(3 downto 0),
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wb_dat_i => slave_i.Dat,
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wb_dat_o => slave_o.dat,
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wb_cyc_i => slave_i.cyc,
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wb_sel_i => slave_i.sel,
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wb_stb_i => slave_i.stb,
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wb_we_i => slave_i.we,
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wb_ack_o => slave_o.ack,
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wb_stall_o => slave_o.stall);
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slave_o.err <= '0';
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slave_o.int <= '0';
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slave_o.rty <= '0';
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end rtl;
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