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70 lines
2.3 KiB
VHDL
70 lines
2.3 KiB
VHDL
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--
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-- This VHDL file was generated by EASE/HDL 7.4 Revision 8 from HDL Works B.V.
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--
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-- Ease library : work
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-- HDL library : work
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-- Host name : ilex
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-- User name : mgebyehu
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-- Time stamp : Wed May 22 13:03:52 2013
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--
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-- Designed by :
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-- Company :
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-- Project info :
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--
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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-- Object : Entity work.DummyMaster
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-- Last modified : Thu Mar 28 16:19:51 2013.
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--------------------------------------------------------------------------------
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library ieee, work, unisim;
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use ieee.std_logic_1164.all;
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use work.endpoint_pkg.all;
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use work.sysc_wbgen2_pkg.all;
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use work.wrcore_pkg.all;
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use work.genram_pkg.all;
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use work.memory_loader_pkg.all;
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use work.wishbone_pkg.all;
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use work.wr_fabric_pkg.all;
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use unisim.VCOMPONENTS.all;
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entity DummyMaster is
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port(
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Master_in : in t_wishbone_master_in;
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Master_o : out t_wishbone_master_out);
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end entity DummyMaster;
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--------------------------------------------------------------------------------
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-- Object : Architecture work.DummyMaster.rtl
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-- Last modified : Thu Mar 28 16:19:51 2013.
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--------------------------------------------------------------------------------
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architecture rtl of DummyMaster is
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begin
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-- master output wishbone signals
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master_o.cyc <= '0';
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master_o.stb <= '0';
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master_o.adr <= (Others => '0');
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master_o.sel <= "0000";
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master_o.we <= '0';
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master_o.dat <= (Others => '0');
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-- Master input wishbone signals
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-- master_i.ack <= '0';
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-- master_i.err <= '0';
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-- master_i.rty <= '0';
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-- master_i.stall <= '0';
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-- master_i.int <= '0';
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-- master_i.dat <= (Others => '0');
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end architecture rtl ; -- of DummyMaster
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