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66 lines
2.3 KiB
VHDL
66 lines
2.3 KiB
VHDL
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--
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-- This VHDL file was generated by EASE/HDL 7.4 Revision 8 from HDL Works B.V.
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--
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-- Ease library : work
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-- HDL library : work
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-- Host name : ilex
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-- User name : mgebyehu
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-- Time stamp : Wed May 22 13:03:52 2013
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--
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-- Designed by :
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-- Company :
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-- Project info :
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--
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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-- Object : Entity work.DummySlave
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-- Last modified : Thu Mar 28 15:49:01 2013.
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--------------------------------------------------------------------------------
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library ieee, work, unisim;
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use ieee.std_logic_1164.all;
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use work.endpoint_pkg.all;
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use work.sysc_wbgen2_pkg.all;
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use work.wrcore_pkg.all;
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use work.genram_pkg.all;
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use work.memory_loader_pkg.all;
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use work.wishbone_pkg.all;
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use work.wr_fabric_pkg.all;
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use unisim.VCOMPONENTS.all;
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entity DummySlave is
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port(
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slave_i : in t_wishbone_slave_in;
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slave_o : out t_wishbone_slave_out);
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end entity DummySlave;
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--------------------------------------------------------------------------------
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-- Object : Architecture work.DummySlave.rtl
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-- Last modified : Thu Mar 28 15:49:01 2013.
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--------------------------------------------------------------------------------
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architecture rtl of DummySlave is
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begin
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-- Slave input wishbone signals
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-- slave_i.cyc <= open;--'0';
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-- slave_i.stb <= open;--'0';
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-- slave_i.adr <= open;--(Others => '0');
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-- slave_i.sel <= open;--"0000";
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-- slave_i.we <= open;--'0';
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-- slave_i.dat <= open;--(Others => '0');
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-- Slave output wishbone signals
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slave_o.ack <= '0';
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slave_o.err <= '0';
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slave_o.rty <= '0';
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slave_o.stall <= '0';
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slave_o.int <= '0';
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slave_o.dat <= (Others => '0');
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end architecture rtl ; -- of DummySlave
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