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67 lines
1.8 KiB
VHDL
67 lines
1.8 KiB
VHDL
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--
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-- This VHDL file was generated by EASE/HDL 7.4 Revision 8 from HDL Works B.V.
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--
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-- Ease library : work
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-- HDL library : work
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-- Host name : ilex
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-- User name : mgebyehu
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-- Time stamp : Wed May 22 13:03:51 2013
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--
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-- Designed by :
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-- Company :
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-- Project info :
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--
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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-- Object : Entity work.LedDrv
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-- Last modified : Tue Apr 09 15:46:24 2013.
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--------------------------------------------------------------------------------
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library ieee, work, unisim;
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use ieee.std_logic_1164.all;
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use work.endpoint_pkg.all;
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use work.sysc_wbgen2_pkg.all;
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use work.wrcore_pkg.all;
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use work.genram_pkg.all;
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use work.memory_loader_pkg.all;
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use work.wishbone_pkg.all;
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use work.wr_fabric_pkg.all;
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use unisim.VCOMPONENTS.all;
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use ieee.std_logic_unsigned.all;
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entity LedDrv is
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port(
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blink : out std_logic;
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clk_sys_i : in std_logic;
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rst_n_i : in std_logic);
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end entity LedDrv;
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--------------------------------------------------------------------------------
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-- Object : Architecture work.LedDrv.structure
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-- Last modified : Tue Apr 09 15:46:24 2013.
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--------------------------------------------------------------------------------
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architecture structure of LedDrv is
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signal counter : std_logic_vector(32 downto 0);
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begin
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blink <= counter(24);
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process(clk_sys_i, rst_n_i)
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begin
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if(rst_n_i = '0') then
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counter <= (others => '0');
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elsif(rising_edge(clk_sys_i)) then
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counter <= counter + 1;
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end if;
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end process;
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end architecture structure ; -- of LedDrv
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