gitified_old_clb_svn/fw/TestDesigns/Watchdog_Valencia/modules/watchdog.vhd

library ieee;
use ieee.std_logic_1164.all;
--use ieee.std_logic_arith.all;
use ieee.numeric_std.all;

entity watchdog is
    generic(
            ARST_LVL : std_logic := '0';                   -- asynchronous reset level
			g_period : integer:=63500
    );
    port   (
            -- wishbone signals
            wb_clk_i      : in  std_logic;                    -- master clock input
            wb_rst_i      : in  std_logic := '0';             -- synchronous active high reset
            arst_i        : in  std_logic := not ARST_LVL;    -- asynchronous reset
            wb_adr_i      : in  std_logic_vector(2 downto 0); -- lower address bits
            wb_dat_i      : in  std_logic_vector(7 downto 0); -- Databus input
            wb_dat_o      : out std_logic_vector(7 downto 0); -- Databus output
            wb_we_i       : in  std_logic;                    -- Write enable input
            wb_stb_i      : in  std_logic;                    -- Strobe signals / core select signal
            wb_cyc_i      : in  std_logic;                    -- Valid bus cycle input
            wb_ack_o      : out std_logic;                    -- Bus cycle acknowledge output
            wb_inta_o     : out std_logic;                    -- interrupt request output signal

            -- watchdog output lines
            multiboot_reset  : out std_logic;                     -- i2c data line output enable, active low
				wd_clk		:out std_logic
    );
end entity watchdog;


architecture structural of watchdog is
    -- registers
    signal prer : unsigned(15 downto 0);             -- clock prescale register
    signal ctr  : std_logic_vector(7 downto 0);      -- control register
    

    -- internal reset signal
    signal rst_i : std_logic;
	
	-- counter signals
	signal cntr_div      : unsigned(23 downto 0);
    signal cntr_tics     : unsigned(31 downto 0);
    signal cntr_overflow : std_logic;

    -- wishbone write access
    signal wb_wacc : std_logic;

    -- internal acknowledge signal
    signal iack_o : std_logic;

  
    -- command register signals
    signal sta, sto, rd, wr, ack, iack : std_logic;

    signal core_en : std_logic;                      -- core enable signal
    signal reset_watchdog,ien     : std_logic;                      -- interrupt enable signal

    

begin
    -- generate internal reset signal
    rst_i <= not wb_rst_i; --arst_i xor ARST_LVL;

    -- generate acknowledge output signal
    gen_ack_o : process(wb_clk_i)
    begin
        if (wb_clk_i'event and wb_clk_i = '1') then
            iack_o <= wb_cyc_i and wb_stb_i and not iack_o;         -- because timing is always honored
        end if;
    end process gen_ack_o;
    wb_ack_o <= iack_o;

    -- generate wishbone write access signal
    wb_wacc <= wb_we_i and iack_o;

    -- assign wb_dat_o
    assign_dato : process(wb_clk_i)
    begin
        if (wb_clk_i'event and wb_clk_i = '1') then
            case wb_adr_i is
                when "000"  => wb_dat_o <= std_logic_vector(prer( 7 downto 0));
                when "001"  => wb_dat_o <= std_logic_vector(prer(15 downto 8));
                when "010"  => wb_dat_o <= ctr;
                --when "011"  => wb_dat_o <= rxr; -- write is transmit register TxR
                --when "100"  => wb_dat_o <= sr;  -- write is command register CR

                -- Debugging registers:
                -- These registers are not documented.
                -- Functionality could change in future releases
                --when "101"  => wb_dat_o <= txr;
                --when "110"  => wb_dat_o <= cr;
                --when "111"  => wb_dat_o <= (others => '0');
                when others => wb_dat_o <= (others => 'X'); -- for simulation only
            end case;
        end if;
    end process assign_dato;


    -- generate registers (CR, SR see below)
    gen_regs: process(rst_i, wb_clk_i)
    begin
        if (rst_i = '0') then
            prer <= (others => '1');
            ctr  <= (others => '0');
           -- txr  <= (others => '0');
        elsif (wb_clk_i'event and wb_clk_i = '1') then
					 if (reset_watchdog = '1') then
						ctr(0)<='0';
					 end if;
               if (wb_rst_i = '1') then
                   prer <= (others => '1');
                   ctr  <= (others => '0');
               --    txr  <= (others => '0');
               elsif (wb_wacc = '1') then
                   case wb_adr_i is
                       when "000" => prer( 7 downto 0) <= unsigned(wb_dat_i);
                       when "001" => prer(15 downto 8) <= unsigned(wb_dat_i);
                       when "010" => ctr               <= wb_dat_i;
                  --     when "011" => txr               <= wb_dat_i;
                       when "100" => null; --write to CR, avoid executing the others clause

                      -- illegal cases, for simulation only
                      when others =>
                          report ("Illegal write address, setting all registers to unknown.");
                          prer <= (others => 'X');
                          ctr  <= (others => 'X');
                    --      txr  <= (others => 'X');
                   end case;
               end if;
        end if;
    end process gen_regs;
   
  --  end block;
	
	
	reset_watchdog <= ctr(0);
	-------------------  TIMER   ---------------------
	
  process(wb_clk_i)
  begin
    if rising_edge(wb_clk_i) then
      if(rst_i = '0') then
        cntr_div      <= (others => '0');
        cntr_overflow <= '0';
      else
        if(cntr_div = g_period-1) then
          cntr_div      <= (others => '0');
          cntr_overflow <= '1';
        else
          cntr_div      <= cntr_div + 1;
          cntr_overflow <= '0';
        end if;
      end if;
    end if;
  end process;

  --usec counter
  process(wb_clk_i)
  begin
    if(rising_edge(wb_clk_i)) then
      if(rst_i = '0') then
        cntr_tics <= (others => '0');
      elsif(cntr_overflow = '1') then
	    if (reset_watchdog = '0') then
            cntr_tics <= cntr_tics + 1;
		else
			cntr_tics <= (others => '0');

		end if;	
		
		if (cntr_tics > prer) then
			multiboot_reset <= '1';
			cntr_tics <= (others => '0');
		else
			multiboot_reset <= '0';
		end if;	
      end if;
    end if;
  end process;
	
	wd_clk<=cntr_tics(0);

end structural;