You've already forked gitified_old_clb_svn
250 lines
39 KiB
Tcl
250 lines
39 KiB
Tcl
onerror {resume}
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quietly virtual signal -install /clb_top_tb/u5/u0/U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/gen_with_packet_filter/U_packet_filter { /clb_top_tb/u5/u0/U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/gen_with_packet_filter/U_packet_filter/ir(28 downto 13)} insn_cmp_value
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quietly virtual signal -install /clb_top_tb/u5/u0/U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/gen_with_packet_filter/U_packet_filter { /clb_top_tb/u5/u0/U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/gen_with_packet_filter/U_packet_filter/ir(12 downto 7)} insn_offset
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quietly WaveActivateNextPane {} 0
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add wave -noupdate /clb_top_tb/MGTCLK_P
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add wave -noupdate /clb_top_tb/button1_i
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add wave -noupdate /clb_top_tb/u5/clk_sys
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add wave -noupdate /clb_top_tb/u5/clk_20m_vcxo_n_i
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add wave -noupdate /clb_top_tb/u5/clk_20m_vcxo_p_i
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add wave -noupdate /clb_top_tb/u5/u4/clk20_vcxo_o
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add wave -noupdate /clb_top_tb/u5/ref_clk_62_5
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add wave -noupdate /clb_top_tb/u5/ref_clk_125
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add wave -noupdate /clb_top_tb/u5/ref_clk_250
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add wave -noupdate -divider LM32_WRPC
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add wave -noupdate /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/clk_sys_i
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add wave -noupdate /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/rst_n_i
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add wave -noupdate -divider Instructions_WRPC
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add wave -noupdate /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/irq_i
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add wave -noupdate -radix hexadecimal /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_o.cyc
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add wave -noupdate -radix hexadecimal /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_o.stb
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add wave -noupdate -radix hexadecimal /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_o.adr
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add wave -noupdate -radix hexadecimal /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_i.ack
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add wave -noupdate -radix hexadecimal /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_o.we
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add wave -noupdate -radix hexadecimal -childformat {{/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_i.dat(31) -radix hexadecimal} {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_i.dat(30) -radix hexadecimal} {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_i.dat(29) -radix hexadecimal} {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_i.dat(28) -radix hexadecimal} {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_i.dat(27) -radix hexadecimal} {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_i.dat(26) -radix hexadecimal} {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_i.dat(25) -radix hexadecimal} {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_i.dat(24) -radix hexadecimal} {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_i.dat(23) -radix hexadecimal} {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_i.dat(22) -radix hexadecimal} {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_i.dat(21) -radix hexadecimal} {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_i.dat(20) -radix hexadecimal} {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_i.dat(19) -radix hexadecimal} {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_i.dat(18) -radix hexadecimal} {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_i.dat(17) -radix hexadecimal} {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_i.dat(16) -radix hexadecimal} {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_i.dat(15) -radix hexadecimal} {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_i.dat(14) -radix hexadecimal} {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_i.dat(13) -radix hexadecimal} {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_i.dat(12) -radix hexadecimal} {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_i.dat(11) -radix hexadecimal} {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_i.dat(10) -radix hexadecimal} {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_i.dat(9) -radix hexadecimal} {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_i.dat(8) -radix hexadecimal} {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_i.dat(7) -radix hexadecimal} {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_i.dat(6) -radix hexadecimal} {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_i.dat(5) -radix hexadecimal} {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_i.dat(4) -radix hexadecimal} {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_i.dat(3) -radix hexadecimal} {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_i.dat(2) -radix hexadecimal} {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_i.dat(1) -radix hexadecimal} {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_i.dat(0) -radix hexadecimal}} -subitemconfig {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_i.dat(31) {-height 15 -radix hexadecimal} /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_i.dat(30) {-height 15 -radix hexadecimal} /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_i.dat(29) {-height 15 -radix hexadecimal} /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_i.dat(28) {-height 15 -radix hexadecimal} /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_i.dat(27) {-height 15 -radix hexadecimal} /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_i.dat(26) {-height 15 -radix hexadecimal} /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_i.dat(25) {-height 15 -radix hexadecimal} /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_i.dat(24) {-height 15 -radix hexadecimal} /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_i.dat(23) {-height 15 -radix hexadecimal} /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_i.dat(22) {-height 15 -radix hexadecimal} /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_i.dat(21) {-height 15 -radix hexadecimal} /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_i.dat(20) {-height 15 -radix hexadecimal} /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_i.dat(19) {-height 15 -radix hexadecimal} /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_i.dat(18) {-height 15 -radix hexadecimal} /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_i.dat(17) {-height 15 -radix hexadecimal} /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_i.dat(16) {-height 15 -radix hexadecimal} /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_i.dat(15) {-height 15 -radix hexadecimal} /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_i.dat(14) {-height 15 -radix hexadecimal} /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_i.dat(13) {-height 15 -radix hexadecimal} /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_i.dat(12) {-height 15 -radix hexadecimal} /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_i.dat(11) {-height 15 -radix hexadecimal} /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_i.dat(10) {-height 15 -radix hexadecimal} /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_i.dat(9) {-height 15 -radix hexadecimal} /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_i.dat(8) {-height 15 -radix hexadecimal} /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_i.dat(7) {-height 15 -radix hexadecimal} /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_i.dat(6) {-height 15 -radix hexadecimal} /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_i.dat(5) {-height 15 -radix hexadecimal} /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_i.dat(4) {-height 15 -radix hexadecimal} /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_i.dat(3) {-height 15 -radix hexadecimal} /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_i.dat(2) {-height 15 -radix hexadecimal} /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_i.dat(1) {-height 15 -radix hexadecimal} /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_i.dat(0) {-height 15 -radix hexadecimal}} /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_i.dat
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add wave -noupdate -radix hexadecimal -childformat {{/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/dwb_i.ack -radix hexadecimal} {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/dwb_i.err -radix hexadecimal} {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/dwb_i.rty -radix hexadecimal} {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/dwb_i.stall -radix hexadecimal} {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/dwb_i.int -radix hexadecimal} {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/dwb_i.dat -radix hexadecimal}} -subitemconfig {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/dwb_i.ack {-height 15 -radix hexadecimal} /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/dwb_i.err {-height 15 -radix hexadecimal} /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/dwb_i.rty {-height 15 -radix hexadecimal} /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/dwb_i.stall {-height 15 -radix hexadecimal} /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/dwb_i.int {-height 15 -radix hexadecimal} /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/dwb_i.dat {-height 15 -radix hexadecimal}} /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/dwb_i
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add wave -noupdate -radix hexadecimal -childformat {{/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/dwb_o.cyc -radix hexadecimal} {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/dwb_o.stb -radix hexadecimal} {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/dwb_o.adr -radix hexadecimal} {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/dwb_o.sel -radix hexadecimal} {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/dwb_o.we -radix hexadecimal} {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/dwb_o.dat -radix hexadecimal}} -subitemconfig {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/dwb_o.cyc {-height 15 -radix hexadecimal} /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/dwb_o.stb {-height 15 -radix hexadecimal} /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/dwb_o.adr {-height 15 -radix hexadecimal} /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/dwb_o.sel {-height 15 -radix hexadecimal} /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/dwb_o.we {-height 15 -radix hexadecimal} /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/dwb_o.dat {-height 15 -radix hexadecimal}} /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/dwb_o
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add wave -noupdate -radix hexadecimal -childformat {{/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_i.ack -radix hexadecimal} {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_i.err -radix hexadecimal} {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_i.rty -radix hexadecimal} {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_i.stall -radix hexadecimal} {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_i.int -radix hexadecimal} {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_i.dat -radix hexadecimal}} -subitemconfig {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_i.ack {-height 15 -radix hexadecimal} /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_i.err {-height 15 -radix hexadecimal} /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_i.rty {-height 15 -radix hexadecimal} /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_i.stall {-height 15 -radix hexadecimal} /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_i.int {-height 15 -radix hexadecimal} /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_i.dat {-height 15 -radix hexadecimal}} /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_i
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add wave -noupdate -radix hexadecimal -childformat {{/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_o.cyc -radix hexadecimal} {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_o.stb -radix hexadecimal} {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_o.adr -radix hexadecimal} {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_o.sel -radix hexadecimal} {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_o.we -radix hexadecimal} {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_o.dat -radix hexadecimal}} -subitemconfig {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_o.cyc {-height 15 -radix hexadecimal} /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_o.stb {-height 15 -radix hexadecimal} /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_o.adr {-height 15 -radix hexadecimal} /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_o.sel {-height 15 -radix hexadecimal} /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_o.we {-height 15 -radix hexadecimal} /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_o.dat {-height 15 -radix hexadecimal}} /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_o
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add wave -noupdate /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug/U_Wrapped_LM32/cpu/reg_0/ram
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add wave -noupdate /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug/U_Wrapped_LM32/cpu/reg_1/ram
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add wave -noupdate -divider Instructions_WRPC
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add wave -noupdate -radix hexadecimal /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug/U_Wrapped_LM32/cpu/decoder/instruction
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add wave -noupdate /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug/U_Wrapped_LM32/cpu/instruction_unit/valid_d
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add wave -noupdate -radix hexadecimal /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug/U_Wrapped_LM32/cpu/instruction_unit/pc_d
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add wave -noupdate -divider WB_CON_WRPC
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add wave -noupdate /clb_top_tb/u5/u0/U_WR_CORE/WRPC/WB_CON/crossbar/c_address
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add wave -noupdate /clb_top_tb/u5/u0/U_WR_CORE/WRPC/WB_CON/slave_i
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add wave -noupdate /clb_top_tb/u5/u0/U_WR_CORE/WRPC/WB_CON/slave_o
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add wave -noupdate /clb_top_tb/u5/u0/U_WR_CORE/WRPC/WB_CON/master_i
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add wave -noupdate /clb_top_tb/u5/u0/U_WR_CORE/WRPC/WB_CON/master_o
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add wave -noupdate /clb_top_tb/u5/u0/U_WR_CORE/WRPC/WB_CON/master_i_1
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add wave -noupdate /clb_top_tb/u5/u0/U_WR_CORE/WRPC/WB_CON/master_o_1
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add wave -noupdate -divider WB_SECONDARY_CON_WRPC
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add wave -noupdate /clb_top_tb/u5/u0/U_WR_CORE/WRPC/WB_SECONDARY_CON/crossbar/c_address
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add wave -noupdate -divider DPRAM_WRPC
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add wave -noupdate /clb_top_tb/u5/u0/U_WR_CORE/WRPC/DPRAM/slave1_i
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add wave -noupdate /clb_top_tb/u5/u0/U_WR_CORE/WRPC/DPRAM/slave1_o
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add wave -noupdate /clb_top_tb/u5/u0/U_WR_CORE/WRPC/DPRAM/slave2_i
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add wave -noupdate /clb_top_tb/u5/u0/U_WR_CORE/WRPC/DPRAM/slave2_o
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add wave -noupdate -divider UART_WRPC
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add wave -noupdate /clb_top_tb/u5/u0/U_WR_CORE/WRPC/PERIPH/UART/clk_sys_i
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add wave -noupdate -radix hexadecimal -childformat {{/clb_top_tb/u5/u0/U_WR_CORE/WRPC/PERIPH/UART/slave_i.cyc -radix hexadecimal} {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/PERIPH/UART/slave_i.stb -radix hexadecimal} {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/PERIPH/UART/slave_i.adr -radix hexadecimal} {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/PERIPH/UART/slave_i.sel -radix hexadecimal} {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/PERIPH/UART/slave_i.we -radix hexadecimal} {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/PERIPH/UART/slave_i.dat -radix hexadecimal}} -subitemconfig {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/PERIPH/UART/slave_i.cyc {-height 15 -radix hexadecimal} /clb_top_tb/u5/u0/U_WR_CORE/WRPC/PERIPH/UART/slave_i.stb {-height 15 -radix hexadecimal} /clb_top_tb/u5/u0/U_WR_CORE/WRPC/PERIPH/UART/slave_i.adr {-height 15 -radix hexadecimal} /clb_top_tb/u5/u0/U_WR_CORE/WRPC/PERIPH/UART/slave_i.sel {-height 15 -radix hexadecimal} /clb_top_tb/u5/u0/U_WR_CORE/WRPC/PERIPH/UART/slave_i.we {-height 15 -radix hexadecimal} /clb_top_tb/u5/u0/U_WR_CORE/WRPC/PERIPH/UART/slave_i.dat {-height 15 -radix hexadecimal}} /clb_top_tb/u5/u0/U_WR_CORE/WRPC/PERIPH/UART/slave_i
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add wave -noupdate /clb_top_tb/u5/u0/U_WR_CORE/WRPC/PERIPH/UART/uart_rxd_i
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add wave -noupdate -radix hexadecimal /clb_top_tb/u5/u0/U_WR_CORE/WRPC/PERIPH/UART/slave_o
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add wave -noupdate /clb_top_tb/u5/u0/U_WR_CORE/WRPC/PERIPH/UART/uart_txd_o
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add wave -noupdate /clb_top_tb/u5/u0/U_WR_CORE/WRPC/PERIPH/UART/rst_n_i
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add wave -noupdate -childformat {{/clb_top_tb/u5/u0/U_WR_CORE/WRPC/PERIPH/UART/U_Wrapped_UART/regs_in.sr_tx_busy_i -radix hexadecimal} {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/PERIPH/UART/U_Wrapped_UART/regs_in.sr_rx_rdy_i -radix hexadecimal} {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/PERIPH/UART/U_Wrapped_UART/regs_in.rdr_rx_data_i -radix hexadecimal} {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/PERIPH/UART/U_Wrapped_UART/regs_in.host_tdr_rdy_i -radix hexadecimal} {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/PERIPH/UART/U_Wrapped_UART/regs_in.host_rdr_data_i -radix hexadecimal} {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/PERIPH/UART/U_Wrapped_UART/regs_in.host_rdr_rdy_i -radix hexadecimal} {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/PERIPH/UART/U_Wrapped_UART/regs_in.host_rdr_count_i -radix hexadecimal}} -subitemconfig {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/PERIPH/UART/U_Wrapped_UART/regs_in.sr_tx_busy_i {-height 15 -radix hexadecimal} /clb_top_tb/u5/u0/U_WR_CORE/WRPC/PERIPH/UART/U_Wrapped_UART/regs_in.sr_rx_rdy_i {-height 15 -radix hexadecimal} /clb_top_tb/u5/u0/U_WR_CORE/WRPC/PERIPH/UART/U_Wrapped_UART/regs_in.rdr_rx_data_i {-height 15 -radix hexadecimal} /clb_top_tb/u5/u0/U_WR_CORE/WRPC/PERIPH/UART/U_Wrapped_UART/regs_in.host_tdr_rdy_i {-height 15 -radix hexadecimal} /clb_top_tb/u5/u0/U_WR_CORE/WRPC/PERIPH/UART/U_Wrapped_UART/regs_in.host_rdr_data_i {-height 15 -radix hexadecimal} /clb_top_tb/u5/u0/U_WR_CORE/WRPC/PERIPH/UART/U_Wrapped_UART/regs_in.host_rdr_rdy_i {-height 15 -radix hexadecimal} /clb_top_tb/u5/u0/U_WR_CORE/WRPC/PERIPH/UART/U_Wrapped_UART/regs_in.host_rdr_count_i {-height 15 -radix hexadecimal}} /clb_top_tb/u5/u0/U_WR_CORE/WRPC/PERIPH/UART/U_Wrapped_UART/regs_in
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add wave -noupdate -divider LM32_2nd
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add wave -noupdate /clb_top_tb/u5/u11/LM32_CORE/clk_sys_i
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add wave -noupdate /clb_top_tb/u5/u11/LM32_CORE/rst_n_i
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add wave -noupdate -divider Instructions_2nd
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add wave -noupdate /clb_top_tb/u5/u11/LM32_CORE/irq_i
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add wave -noupdate -radix hexadecimal /clb_top_tb/u5/u11/LM32_CORE/iwb_o.cyc
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add wave -noupdate -radix hexadecimal /clb_top_tb/u5/u11/LM32_CORE/iwb_o.stb
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add wave -noupdate -radix hexadecimal /clb_top_tb/u5/u11/LM32_CORE/iwb_o.adr
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add wave -noupdate -radix hexadecimal /clb_top_tb/u5/u11/LM32_CORE/iwb_i.ack
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add wave -noupdate -radix hexadecimal /clb_top_tb/u5/u11/LM32_CORE/iwb_o.we
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add wave -noupdate -radix hexadecimal -childformat {{/clb_top_tb/u5/u11/LM32_CORE/iwb_i.dat(31) -radix hexadecimal} {/clb_top_tb/u5/u11/LM32_CORE/iwb_i.dat(30) -radix hexadecimal} {/clb_top_tb/u5/u11/LM32_CORE/iwb_i.dat(29) -radix hexadecimal} {/clb_top_tb/u5/u11/LM32_CORE/iwb_i.dat(28) -radix hexadecimal} {/clb_top_tb/u5/u11/LM32_CORE/iwb_i.dat(27) -radix hexadecimal} {/clb_top_tb/u5/u11/LM32_CORE/iwb_i.dat(26) -radix hexadecimal} {/clb_top_tb/u5/u11/LM32_CORE/iwb_i.dat(25) -radix hexadecimal} {/clb_top_tb/u5/u11/LM32_CORE/iwb_i.dat(24) -radix hexadecimal} {/clb_top_tb/u5/u11/LM32_CORE/iwb_i.dat(23) -radix hexadecimal} {/clb_top_tb/u5/u11/LM32_CORE/iwb_i.dat(22) -radix hexadecimal} {/clb_top_tb/u5/u11/LM32_CORE/iwb_i.dat(21) -radix hexadecimal} {/clb_top_tb/u5/u11/LM32_CORE/iwb_i.dat(20) -radix hexadecimal} {/clb_top_tb/u5/u11/LM32_CORE/iwb_i.dat(19) -radix hexadecimal} {/clb_top_tb/u5/u11/LM32_CORE/iwb_i.dat(18) -radix hexadecimal} {/clb_top_tb/u5/u11/LM32_CORE/iwb_i.dat(17) -radix hexadecimal} {/clb_top_tb/u5/u11/LM32_CORE/iwb_i.dat(16) -radix hexadecimal} {/clb_top_tb/u5/u11/LM32_CORE/iwb_i.dat(15) -radix hexadecimal} {/clb_top_tb/u5/u11/LM32_CORE/iwb_i.dat(14) -radix hexadecimal} {/clb_top_tb/u5/u11/LM32_CORE/iwb_i.dat(13) -radix hexadecimal} {/clb_top_tb/u5/u11/LM32_CORE/iwb_i.dat(12) -radix hexadecimal} {/clb_top_tb/u5/u11/LM32_CORE/iwb_i.dat(11) -radix hexadecimal} {/clb_top_tb/u5/u11/LM32_CORE/iwb_i.dat(10) -radix hexadecimal} {/clb_top_tb/u5/u11/LM32_CORE/iwb_i.dat(9) -radix hexadecimal} {/clb_top_tb/u5/u11/LM32_CORE/iwb_i.dat(8) -radix hexadecimal} {/clb_top_tb/u5/u11/LM32_CORE/iwb_i.dat(7) -radix hexadecimal} {/clb_top_tb/u5/u11/LM32_CORE/iwb_i.dat(6) -radix hexadecimal} {/clb_top_tb/u5/u11/LM32_CORE/iwb_i.dat(5) -radix hexadecimal} {/clb_top_tb/u5/u11/LM32_CORE/iwb_i.dat(4) -radix hexadecimal} {/clb_top_tb/u5/u11/LM32_CORE/iwb_i.dat(3) -radix hexadecimal} {/clb_top_tb/u5/u11/LM32_CORE/iwb_i.dat(2) -radix hexadecimal} {/clb_top_tb/u5/u11/LM32_CORE/iwb_i.dat(1) -radix hexadecimal} {/clb_top_tb/u5/u11/LM32_CORE/iwb_i.dat(0) -radix hexadecimal}} -subitemconfig {/clb_top_tb/u5/u11/LM32_CORE/iwb_i.dat(31) {-height 15 -radix hexadecimal} /clb_top_tb/u5/u11/LM32_CORE/iwb_i.dat(30) {-height 15 -radix hexadecimal} /clb_top_tb/u5/u11/LM32_CORE/iwb_i.dat(29) {-height 15 -radix hexadecimal} /clb_top_tb/u5/u11/LM32_CORE/iwb_i.dat(28) {-height 15 -radix hexadecimal} /clb_top_tb/u5/u11/LM32_CORE/iwb_i.dat(27) {-height 15 -radix hexadecimal} /clb_top_tb/u5/u11/LM32_CORE/iwb_i.dat(26) {-height 15 -radix hexadecimal} /clb_top_tb/u5/u11/LM32_CORE/iwb_i.dat(25) {-height 15 -radix hexadecimal} /clb_top_tb/u5/u11/LM32_CORE/iwb_i.dat(24) {-height 15 -radix hexadecimal} /clb_top_tb/u5/u11/LM32_CORE/iwb_i.dat(23) {-height 15 -radix hexadecimal} /clb_top_tb/u5/u11/LM32_CORE/iwb_i.dat(22) {-height 15 -radix hexadecimal} /clb_top_tb/u5/u11/LM32_CORE/iwb_i.dat(21) {-height 15 -radix hexadecimal} /clb_top_tb/u5/u11/LM32_CORE/iwb_i.dat(20) {-height 15 -radix hexadecimal} /clb_top_tb/u5/u11/LM32_CORE/iwb_i.dat(19) {-height 15 -radix hexadecimal} /clb_top_tb/u5/u11/LM32_CORE/iwb_i.dat(18) {-height 15 -radix hexadecimal} /clb_top_tb/u5/u11/LM32_CORE/iwb_i.dat(17) {-height 15 -radix hexadecimal} /clb_top_tb/u5/u11/LM32_CORE/iwb_i.dat(16) {-height 15 -radix hexadecimal} /clb_top_tb/u5/u11/LM32_CORE/iwb_i.dat(15) {-height 15 -radix hexadecimal} /clb_top_tb/u5/u11/LM32_CORE/iwb_i.dat(14) {-height 15 -radix hexadecimal} /clb_top_tb/u5/u11/LM32_CORE/iwb_i.dat(13) {-height 15 -radix hexadecimal} /clb_top_tb/u5/u11/LM32_CORE/iwb_i.dat(12) {-height 15 -radix hexadecimal} /clb_top_tb/u5/u11/LM32_CORE/iwb_i.dat(11) {-height 15 -radix hexadecimal} /clb_top_tb/u5/u11/LM32_CORE/iwb_i.dat(10) {-height 15 -radix hexadecimal} /clb_top_tb/u5/u11/LM32_CORE/iwb_i.dat(9) {-height 15 -radix hexadecimal} /clb_top_tb/u5/u11/LM32_CORE/iwb_i.dat(8) {-height 15 -radix hexadecimal} /clb_top_tb/u5/u11/LM32_CORE/iwb_i.dat(7) {-height 15 -radix hexadecimal} /clb_top_tb/u5/u11/LM32_CORE/iwb_i.dat(6) {-height 15 -radix hexadecimal} /clb_top_tb/u5/u11/LM32_CORE/iwb_i.dat(5) {-height 15 -radix hexadecimal} /clb_top_tb/u5/u11/LM32_CORE/iwb_i.dat(4) {-height 15 -radix hexadecimal} /clb_top_tb/u5/u11/LM32_CORE/iwb_i.dat(3) {-height 15 -radix hexadecimal} /clb_top_tb/u5/u11/LM32_CORE/iwb_i.dat(2) {-height 15 -radix hexadecimal} /clb_top_tb/u5/u11/LM32_CORE/iwb_i.dat(1) {-height 15 -radix hexadecimal} /clb_top_tb/u5/u11/LM32_CORE/iwb_i.dat(0) {-height 15 -radix hexadecimal}} /clb_top_tb/u5/u11/LM32_CORE/iwb_i.dat
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add wave -noupdate -radix hexadecimal -childformat {{/clb_top_tb/u5/u11/LM32_CORE/dwb_i.ack -radix hexadecimal} {/clb_top_tb/u5/u11/LM32_CORE/dwb_i.err -radix hexadecimal} {/clb_top_tb/u5/u11/LM32_CORE/dwb_i.rty -radix hexadecimal} {/clb_top_tb/u5/u11/LM32_CORE/dwb_i.stall -radix hexadecimal} {/clb_top_tb/u5/u11/LM32_CORE/dwb_i.int -radix hexadecimal} {/clb_top_tb/u5/u11/LM32_CORE/dwb_i.dat -radix hexadecimal}} -subitemconfig {/clb_top_tb/u5/u11/LM32_CORE/dwb_i.ack {-height 15 -radix hexadecimal} /clb_top_tb/u5/u11/LM32_CORE/dwb_i.err {-height 15 -radix hexadecimal} /clb_top_tb/u5/u11/LM32_CORE/dwb_i.rty {-height 15 -radix hexadecimal} /clb_top_tb/u5/u11/LM32_CORE/dwb_i.stall {-height 15 -radix hexadecimal} /clb_top_tb/u5/u11/LM32_CORE/dwb_i.int {-height 15 -radix hexadecimal} /clb_top_tb/u5/u11/LM32_CORE/dwb_i.dat {-height 15 -radix hexadecimal}} /clb_top_tb/u5/u11/LM32_CORE/dwb_i
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add wave -noupdate -radix hexadecimal -childformat {{/clb_top_tb/u5/u11/LM32_CORE/dwb_o.cyc -radix hexadecimal} {/clb_top_tb/u5/u11/LM32_CORE/dwb_o.stb -radix hexadecimal} {/clb_top_tb/u5/u11/LM32_CORE/dwb_o.adr -radix hexadecimal} {/clb_top_tb/u5/u11/LM32_CORE/dwb_o.sel -radix hexadecimal} {/clb_top_tb/u5/u11/LM32_CORE/dwb_o.we -radix hexadecimal} {/clb_top_tb/u5/u11/LM32_CORE/dwb_o.dat -radix hexadecimal}} -subitemconfig {/clb_top_tb/u5/u11/LM32_CORE/dwb_o.cyc {-height 15 -radix hexadecimal} /clb_top_tb/u5/u11/LM32_CORE/dwb_o.stb {-height 15 -radix hexadecimal} /clb_top_tb/u5/u11/LM32_CORE/dwb_o.adr {-height 15 -radix hexadecimal} /clb_top_tb/u5/u11/LM32_CORE/dwb_o.sel {-height 15 -radix hexadecimal} /clb_top_tb/u5/u11/LM32_CORE/dwb_o.we {-height 15 -radix hexadecimal} /clb_top_tb/u5/u11/LM32_CORE/dwb_o.dat {-height 15 -radix hexadecimal}} /clb_top_tb/u5/u11/LM32_CORE/dwb_o
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add wave -noupdate -radix hexadecimal -childformat {{/clb_top_tb/u5/u11/LM32_CORE/iwb_i.ack -radix hexadecimal} {/clb_top_tb/u5/u11/LM32_CORE/iwb_i.err -radix hexadecimal} {/clb_top_tb/u5/u11/LM32_CORE/iwb_i.rty -radix hexadecimal} {/clb_top_tb/u5/u11/LM32_CORE/iwb_i.stall -radix hexadecimal} {/clb_top_tb/u5/u11/LM32_CORE/iwb_i.int -radix hexadecimal} {/clb_top_tb/u5/u11/LM32_CORE/iwb_i.dat -radix hexadecimal}} -subitemconfig {/clb_top_tb/u5/u11/LM32_CORE/iwb_i.ack {-height 15 -radix hexadecimal} /clb_top_tb/u5/u11/LM32_CORE/iwb_i.err {-height 15 -radix hexadecimal} /clb_top_tb/u5/u11/LM32_CORE/iwb_i.rty {-height 15 -radix hexadecimal} /clb_top_tb/u5/u11/LM32_CORE/iwb_i.stall {-height 15 -radix hexadecimal} /clb_top_tb/u5/u11/LM32_CORE/iwb_i.int {-height 15 -radix hexadecimal} /clb_top_tb/u5/u11/LM32_CORE/iwb_i.dat {-height 15 -radix hexadecimal}} /clb_top_tb/u5/u11/LM32_CORE/iwb_i
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add wave -noupdate -radix hexadecimal -childformat {{/clb_top_tb/u5/u11/LM32_CORE/iwb_o.cyc -radix hexadecimal} {/clb_top_tb/u5/u11/LM32_CORE/iwb_o.stb -radix hexadecimal} {/clb_top_tb/u5/u11/LM32_CORE/iwb_o.adr -radix hexadecimal} {/clb_top_tb/u5/u11/LM32_CORE/iwb_o.sel -radix hexadecimal} {/clb_top_tb/u5/u11/LM32_CORE/iwb_o.we -radix hexadecimal} {/clb_top_tb/u5/u11/LM32_CORE/iwb_o.dat -radix hexadecimal}} -subitemconfig {/clb_top_tb/u5/u11/LM32_CORE/iwb_o.cyc {-height 15 -radix hexadecimal} /clb_top_tb/u5/u11/LM32_CORE/iwb_o.stb {-height 15 -radix hexadecimal} /clb_top_tb/u5/u11/LM32_CORE/iwb_o.adr {-height 15 -radix hexadecimal} /clb_top_tb/u5/u11/LM32_CORE/iwb_o.sel {-height 15 -radix hexadecimal} /clb_top_tb/u5/u11/LM32_CORE/iwb_o.we {-height 15 -radix hexadecimal} /clb_top_tb/u5/u11/LM32_CORE/iwb_o.dat {-height 15 -radix hexadecimal}} /clb_top_tb/u5/u11/LM32_CORE/iwb_o
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add wave -noupdate /clb_top_tb/u5/u11/LM32_CORE/gen_profile_medium_icache_debug/U_Wrapped_LM32/cpu/reg_0/ram
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add wave -noupdate /clb_top_tb/u5/u11/LM32_CORE/gen_profile_medium_icache_debug/U_Wrapped_LM32/cpu/reg_1/ram
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add wave -noupdate -divider Instructions_2nd
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add wave -noupdate -radix hexadecimal /clb_top_tb/u5/u11/LM32_CORE/gen_profile_medium_icache_debug/U_Wrapped_LM32/cpu/decoder/instruction
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add wave -noupdate /clb_top_tb/u5/u11/LM32_CORE/gen_profile_medium_icache_debug/U_Wrapped_LM32/cpu/instruction_unit/valid_d
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add wave -noupdate -radix hexadecimal /clb_top_tb/u5/u11/LM32_CORE/gen_profile_medium_icache_debug/U_Wrapped_LM32/cpu/instruction_unit/pc_d
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add wave -noupdate -divider WB_CON_2nd
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add wave -noupdate /clb_top_tb/u5/u11/WB_CON/crossbar/c_address
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add wave -noupdate /clb_top_tb/u5/u11/WB_CON/slave_i
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add wave -noupdate /clb_top_tb/u5/u11/WB_CON/slave_o
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add wave -noupdate /clb_top_tb/u5/u11/WB_CON/master_i
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add wave -noupdate -expand -subitemconfig {/clb_top_tb/u5/u11/WB_CON/master_o(2) -expand} /clb_top_tb/u5/u11/WB_CON/master_o
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add wave -noupdate /clb_top_tb/u5/u11/WB_CON/master_i_1
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add wave -noupdate /clb_top_tb/u5/u11/WB_CON/master_o_1
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add wave -noupdate -divider WB_SECONDARY_CON_2nd
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add wave -noupdate /clb_top_tb/u5/u11/WB_SECONDARY_CON/crossbar/c_address
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add wave -noupdate -divider DPRAM_2nd
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add wave -noupdate /clb_top_tb/u5/u11/DPRAM/slave1_i
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add wave -noupdate /clb_top_tb/u5/u11/DPRAM/slave1_o
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add wave -noupdate /clb_top_tb/u5/u11/DPRAM/slave2_i
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add wave -noupdate /clb_top_tb/u5/u11/DPRAM/slave2_o
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add wave -noupdate -divider UART_2nd
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add wave -noupdate /clb_top_tb/u5/u11/u12/clk_sys_i
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add wave -noupdate -radix hexadecimal -childformat {{/clb_top_tb/u5/u11/u12/slave_i.cyc -radix hexadecimal} {/clb_top_tb/u5/u11/u12/slave_i.stb -radix hexadecimal} {/clb_top_tb/u5/u11/u12/slave_i.adr -radix hexadecimal} {/clb_top_tb/u5/u11/u12/slave_i.sel -radix hexadecimal} {/clb_top_tb/u5/u11/u12/slave_i.we -radix hexadecimal} {/clb_top_tb/u5/u11/u12/slave_i.dat -radix hexadecimal}} -subitemconfig {/clb_top_tb/u5/u11/u12/slave_i.cyc {-height 15 -radix hexadecimal} /clb_top_tb/u5/u11/u12/slave_i.stb {-height 15 -radix hexadecimal} /clb_top_tb/u5/u11/u12/slave_i.adr {-height 15 -radix hexadecimal} /clb_top_tb/u5/u11/u12/slave_i.sel {-height 15 -radix hexadecimal} /clb_top_tb/u5/u11/u12/slave_i.we {-height 15 -radix hexadecimal} /clb_top_tb/u5/u11/u12/slave_i.dat {-height 15 -radix hexadecimal}} /clb_top_tb/u5/u11/u12/slave_i
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add wave -noupdate /clb_top_tb/u5/u11/u12/uart_rxd_i
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add wave -noupdate -radix hexadecimal /clb_top_tb/u5/u11/u12/slave_o
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add wave -noupdate /clb_top_tb/u5/u11/u12/uart_txd_o
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add wave -noupdate /clb_top_tb/u5/u11/u12/rst_n_i
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add wave -noupdate /clb_top_tb/u5/u11/u12/U_Wrapped_UART/regs_in
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add wave -noupdate -divider {TransmitFrame 16 Bit}
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add wave -noupdate /clb_top_tb/u2/Clk
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add wave -noupdate /clb_top_tb/u2/tx_data_swap
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add wave -noupdate /clb_top_tb/u2/Rx_Fire
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add wave -noupdate /clb_top_tb/u2/Rx_CRC_Err
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add wave -noupdate /clb_top_tb/u2/TxCharIsK
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add wave -noupdate /clb_top_tb/u2/TxData
|
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add wave -noupdate /clb_top_tb/u2/state
|
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add wave -noupdate /clb_top_tb/u2/CRCOut
|
|
add wave -noupdate -divider {IPMUX PauseReqLogic}
|
|
add wave -noupdate /clb_top_tb/u5/u5/u6/u2/PauseAck
|
|
add wave -noupdate /clb_top_tb/u5/u5/u6/u2/PauseReq
|
|
add wave -noupdate -radix hexadecimal /clb_top_tb/u5/u5/u6/u2/PauseVal
|
|
add wave -noupdate /clb_top_tb/u5/u5/u6/u2/WaterMarkHigh
|
|
add wave -noupdate /clb_top_tb/u5/u5/u6/u2/WaterMarkLow
|
|
add wave -noupdate -divider xwrf_mux
|
|
add wave -noupdate /clb_top_tb/u5/u0/U_WR_CORE/WRPC/U_WBP_MUX/ep_snk_i
|
|
add wave -noupdate /clb_top_tb/u5/u0/U_WR_CORE/WRPC/U_WBP_MUX/ep_snk_o
|
|
add wave -noupdate /clb_top_tb/u5/u0/U_WR_CORE/WRPC/U_WBP_MUX/ep_src_i
|
|
add wave -noupdate /clb_top_tb/u5/u0/U_WR_CORE/WRPC/U_WBP_MUX/ep_src_o
|
|
add wave -noupdate /clb_top_tb/u5/u0/U_WR_CORE/WRPC/U_WBP_MUX/mux_select
|
|
add wave -noupdate /clb_top_tb/u5/u0/U_WR_CORE/WRPC/U_WBP_MUX/mux_snk_i
|
|
add wave -noupdate /clb_top_tb/u5/u0/U_WR_CORE/WRPC/U_WBP_MUX/mux_snk_o
|
|
add wave -noupdate -expand -subitemconfig {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/U_WBP_MUX/mux_src_o(1) {-height 15 -childformat {{/clb_top_tb/u5/u0/U_WR_CORE/WRPC/U_WBP_MUX/mux_src_o(1).dat -radix hexadecimal}} -expand} /clb_top_tb/u5/u0/U_WR_CORE/WRPC/U_WBP_MUX/mux_src_o(1).dat {-height 15 -radix hexadecimal}} /clb_top_tb/u5/u0/U_WR_CORE/WRPC/U_WBP_MUX/mux_src_o
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add wave -noupdate -expand -subitemconfig {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/U_WBP_MUX/mux_src_i(1) -expand} /clb_top_tb/u5/u0/U_WR_CORE/WRPC/U_WBP_MUX/mux_src_i
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add wave -noupdate -divider TxFire
|
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add wave -noupdate /clb_top_tb/u5/u8/Clk
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add wave -noupdate -expand /clb_top_tb/u5/u8/Fire
|
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add wave -noupdate -expand -subitemconfig {/clb_top_tb/u5/u8/UDP_Tx(0) -expand} /clb_top_tb/u5/u8/UDP_Tx
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add wave -noupdate /clb_top_tb/u5/u8/UDP_Tx_Full
|
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add wave -noupdate -expand /clb_top_tb/u5/u8/UDP_Tx_WrReq
|
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add wave -noupdate -divider ipmux_wrf_src
|
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add wave -noupdate /clb_top_tb/u5/u5/u0/u3/Clk
|
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add wave -noupdate /clb_top_tb/u5/u5/u0/u3/Din
|
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add wave -noupdate /clb_top_tb/u5/u5/u0/u3/EOP
|
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add wave -noupdate /clb_top_tb/u5/u5/u0/u3/Empty
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add wave -noupdate /clb_top_tb/u5/u5/u0/u3/Offset
|
|
add wave -noupdate -radix hexadecimal /clb_top_tb/u5/u5/u0/u3/PktPtr
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add wave -noupdate -radix hexadecimal /clb_top_tb/u5/u5/u0/u3/PktRdPtr
|
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add wave -noupdate -radix hexadecimal /clb_top_tb/u5/u5/u0/u3/RdAddr
|
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add wave -noupdate /clb_top_tb/u5/u5/u0/u3/state
|
|
add wave -noupdate -childformat {{/clb_top_tb/u5/u5/u0/u3/src_o.adr -radix hexadecimal} {/clb_top_tb/u5/u5/u0/u3/src_o.dat -radix hexadecimal}} -expand -subitemconfig {/clb_top_tb/u5/u5/u0/u3/src_o.adr {-height 15 -radix hexadecimal} /clb_top_tb/u5/u5/u0/u3/src_o.dat {-height 15 -radix hexadecimal}} /clb_top_tb/u5/u5/u0/u3/src_o
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|
add wave -noupdate -expand /clb_top_tb/u5/u5/u0/u3/src_i
|
|
add wave -noupdate -divider ReceivedInTestbench_PHY
|
|
add wave -noupdate -radix hexadecimal /clb_top_tb/u1/rx_k_o
|
|
add wave -noupdate -radix hexadecimal /clb_top_tb/u1/rx_data_o
|
|
add wave -noupdate /clb_top_tb/u1/rx_rbclk_o
|
|
add wave -noupdate -divider ipmux_wrf_snk
|
|
add wave -noupdate /clb_top_tb/u5/u5/u6/u1/Clk
|
|
add wave -noupdate -expand /clb_top_tb/u5/u5/u6/u1/snk_i
|
|
add wave -noupdate /clb_top_tb/u5/u5/u6/u1/We_Int
|
|
add wave -noupdate /clb_top_tb/u5/u5/u6/u1/snk_o
|
|
add wave -noupdate /clb_top_tb/u5/u5/u6/u1/rd_req
|
|
add wave -noupdate /clb_top_tb/u5/u5/u6/u1/stall_int
|
|
add wave -noupdate /clb_top_tb/u5/u5/u6/u1/q_adr_p1
|
|
add wave -noupdate /clb_top_tb/u5/u5/u6/u1/q_data_p1
|
|
add wave -noupdate /clb_top_tb/u5/u5/u6/u1/q_valid_p1
|
|
add wave -noupdate /clb_top_tb/u5/u5/u6/u1/snk_valid
|
|
add wave -noupdate /clb_top_tb/u5/u5/u6/u1/adr_change
|
|
add wave -noupdate /clb_top_tb/u5/u5/u6/u1/eocycle
|
|
add wave -noupdate /clb_top_tb/u5/u5/u6/u1/shift_pipeline
|
|
add wave -noupdate /clb_top_tb/u5/u5/u6/u1/good_frame
|
|
add wave -noupdate /clb_top_tb/u5/u5/u6/u1/bad_frame
|
|
add wave -noupdate /clb_top_tb/u5/u5/u6/u1/Dout
|
|
add wave -noupdate /clb_top_tb/u5/u5/u6/u1/EOF
|
|
add wave -noupdate /clb_top_tb/u5/u5/u6/u1/Full
|
|
add wave -noupdate /clb_top_tb/u5/u5/u6/u1/Offset
|
|
add wave -noupdate /clb_top_tb/u5/u5/u6/u1/OverFlow
|
|
add wave -noupdate /clb_top_tb/u5/u5/u6/u1/PktPtr
|
|
add wave -noupdate /clb_top_tb/u5/u5/u6/u1/PktWrPtr
|
|
add wave -noupdate /clb_top_tb/u5/u5/u6/u1/We
|
|
add wave -noupdate /clb_top_tb/u5/u5/u6/u1/WrAddr
|
|
add wave -noupdate /clb_top_tb/u5/u5/u6/u1/abits
|
|
add wave -noupdate /clb_top_tb/u5/u5/u6/u1/snk_cyc_d0
|
|
add wave -noupdate -divider ep_timestamping_unit
|
|
add wave -noupdate /clb_top_tb/u5/u0/U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_EP_TSU/clk_ref_i
|
|
add wave -noupdate /clb_top_tb/u5/u0/U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_EP_TSU/clk_sys_i
|
|
add wave -noupdate /clb_top_tb/u5/SFP_TX_P
|
|
add wave -noupdate -radix hexadecimal /clb_top_tb/u5/u0/U_GTP/tx_data_i
|
|
add wave -noupdate /clb_top_tb/u5/u0/U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_EP_TSU/tx_ts_done
|
|
add wave -noupdate /clb_top_tb/u5/txts_o
|
|
add wave -noupdate -radix hexadecimal /clb_top_tb/u5/u0/U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_EP_TSU/txts_timestamp_o
|
|
add wave -noupdate /clb_top_tb/u5/u0/U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_EP_TSU/clk_rx_i
|
|
add wave -noupdate /clb_top_tb/u5/SFP_RX_P
|
|
add wave -noupdate -radix hexadecimal /clb_top_tb/u5/u0/U_GTP/rx_data_o
|
|
add wave -noupdate /clb_top_tb/u5/u0/U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_EP_TSU/rx_ts_done
|
|
add wave -noupdate /clb_top_tb/u5/rxts_o
|
|
add wave -noupdate -radix hexadecimal /clb_top_tb/u5/u0/U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_EP_TSU/rxts_timestamp_o
|
|
add wave -noupdate /clb_top_tb/u5/bitslide
|
|
add wave -noupdate -divider EndpointRegisters
|
|
add wave -noupdate /clb_top_tb/u5/u0/U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/regs_fromwb
|
|
add wave -noupdate /clb_top_tb/u5/u0/U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/regs_towb
|
|
add wave -noupdate /clb_top_tb/u5/u0/rxts_o
|
|
add wave -noupdate /clb_top_tb/u5/u0/txts_o
|
|
add wave -noupdate -divider PHY
|
|
add wave -noupdate /clb_top_tb/u5/u0/U_GTP/rx_k_o
|
|
add wave -noupdate -radix hexadecimal /clb_top_tb/u5/u0/U_GTP/rx_data_o
|
|
add wave -noupdate -radix hexadecimal /clb_top_tb/u5/u0/U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit/U_RX_PCS/an_rx_val_o
|
|
add wave -noupdate /clb_top_tb/u5/u0/U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit/U_RX_PCS/an_rx_valid_o
|
|
add wave -noupdate /clb_top_tb/u5/u0/U_GTP/tx_k_i
|
|
add wave -noupdate -radix hexadecimal /clb_top_tb/u5/u0/U_GTP/tx_data_i
|
|
add wave -noupdate -radix hexadecimal /clb_top_tb/u5/u0/U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit/U_TX_PCS/an_tx_val_i
|
|
add wave -noupdate /clb_top_tb/u5/u0/U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit/U_TX_PCS/an_tx_en_i
|
|
add wave -noupdate -divider ipmux_Registers
|
|
add wave -noupdate /clb_top_tb/u5/u5/u4/Clk
|
|
add wave -noupdate /clb_top_tb/u5/u5/u4/Rst
|
|
add wave -noupdate -expand /clb_top_tb/u5/u5/u4/wb_ipmux_reg_i
|
|
add wave -noupdate -expand /clb_top_tb/u5/u5/u4/wb_ipmux_reg_o
|
|
add wave -noupdate -childformat {{/clb_top_tb/u5/u5/u4/eth_regs_o.MAC_Mod -radix hexadecimal} {/clb_top_tb/u5/u5/u4/eth_regs_o.MAC_Srv -radix hexadecimal} {/clb_top_tb/u5/u5/u4/eth_regs_o.IP_Mod -radix hexadecimal} {/clb_top_tb/u5/u5/u4/eth_regs_o.IP_Srv -radix hexadecimal} {/clb_top_tb/u5/u5/u4/eth_regs_o.UDP_SrvPrt -radix hexadecimal} {/clb_top_tb/u5/u5/u4/eth_regs_o.UDP_ModPrt -radix hexadecimal}} -expand -subitemconfig {/clb_top_tb/u5/u5/u4/eth_regs_o.MAC_Mod {-height 15 -radix hexadecimal} /clb_top_tb/u5/u5/u4/eth_regs_o.MAC_Srv {-height 15 -radix hexadecimal} /clb_top_tb/u5/u5/u4/eth_regs_o.IP_Mod {-height 15 -radix hexadecimal} /clb_top_tb/u5/u5/u4/eth_regs_o.IP_Srv {-height 15 -radix hexadecimal} /clb_top_tb/u5/u5/u4/eth_regs_o.UDP_SrvPrt {-height 15 -radix hexadecimal} /clb_top_tb/u5/u5/u4/eth_regs_o.UDP_ModPrt {-height 15 -radix hexadecimal}} /clb_top_tb/u5/u5/u4/eth_regs_o
|
|
add wave -noupdate -radix hexadecimal /clb_top_tb/u5/u5/u4/IP_Mod
|
|
add wave -noupdate -radix hexadecimal /clb_top_tb/u5/u5/u4/IP_Srv
|
|
add wave -noupdate -radix hexadecimal /clb_top_tb/u5/u5/u4/MAC_Mod
|
|
add wave -noupdate -radix hexadecimal /clb_top_tb/u5/u5/u4/MAC_Srv
|
|
add wave -noupdate -radix hexadecimal /clb_top_tb/u5/u5/u4/UDP_ModPrt
|
|
add wave -noupdate -radix hexadecimal /clb_top_tb/u5/u5/u4/UDP_SrvPrt
|
|
add wave -noupdate -divider ipmux_rxfifos
|
|
add wave -noupdate /clb_top_tb/u5/u5/u7/Empty
|
|
add wave -noupdate /clb_top_tb/u5/u5/u7/RXi
|
|
add wave -noupdate -childformat {{/clb_top_tb/u5/u5/u7/RXo(4) -radix hexadecimal} {/clb_top_tb/u5/u5/u7/RXo(3) -radix hexadecimal} {/clb_top_tb/u5/u5/u7/RXo(2) -radix hexadecimal} {/clb_top_tb/u5/u5/u7/RXo(1) -radix hexadecimal} {/clb_top_tb/u5/u5/u7/RXo(0) -radix hexadecimal}} -expand -subitemconfig {/clb_top_tb/u5/u5/u7/RXo(4) {-height 15 -radix hexadecimal} /clb_top_tb/u5/u5/u7/RXo(3) {-height 15 -radix hexadecimal} /clb_top_tb/u5/u5/u7/RXo(2) {-height 15 -radix hexadecimal} /clb_top_tb/u5/u5/u7/RXo(1) {-height 15 -radix hexadecimal} /clb_top_tb/u5/u5/u7/RXo(0) {-height 15 -radix hexadecimal}} /clb_top_tb/u5/u5/u7/RXo
|
|
add wave -noupdate -expand /clb_top_tb/u5/u5/u7/RdReq
|
|
add wave -noupdate /clb_top_tb/u5/u5/u7/WrReq
|
|
add wave -noupdate -divider ipmux_registers_txrx
|
|
add wave -noupdate /clb_top_tb/u5/u5/u4/cpu_rdreq
|
|
add wave -noupdate -childformat {{/clb_top_tb/u5/u5/u4/cpu_rx.D -radix hexadecimal}} -expand -subitemconfig {/clb_top_tb/u5/u5/u4/cpu_rx.D {-height 15 -radix hexadecimal}} /clb_top_tb/u5/u5/u4/cpu_rx
|
|
add wave -noupdate -childformat {{/clb_top_tb/u5/u5/u4/wb_ipmux_rx_tx_i.dat -radix hexadecimal}} -expand -subitemconfig {/clb_top_tb/u5/u5/u4/wb_ipmux_rx_tx_i.dat {-height 15 -radix hexadecimal}} /clb_top_tb/u5/u5/u4/wb_ipmux_rx_tx_i
|
|
add wave -noupdate -childformat {{/clb_top_tb/u5/u5/u4/wb_ipmux_rx_tx_o.dat -radix hexadecimal}} -expand -subitemconfig {/clb_top_tb/u5/u5/u4/wb_ipmux_rx_tx_o.dat {-height 15 -radix hexadecimal}} /clb_top_tb/u5/u5/u4/wb_ipmux_rx_tx_o
|
|
add wave -noupdate /clb_top_tb/u5/u5/u4/CPU_AccGnt
|
|
add wave -noupdate -childformat {{/clb_top_tb/u5/u5/u4/CPU_Tx.D -radix hexadecimal} {/clb_top_tb/u5/u5/u4/CPU_Tx.Addr -radix hexadecimal}} -expand -subitemconfig {/clb_top_tb/u5/u5/u4/CPU_Tx.D {-height 15 -radix hexadecimal} /clb_top_tb/u5/u5/u4/CPU_Tx.Addr {-height 15 -radix hexadecimal}} /clb_top_tb/u5/u5/u4/CPU_Tx
|
|
add wave -noupdate /clb_top_tb/u5/u5/u4/wr_tx
|
|
add wave -noupdate /clb_top_tb/u5/u5/u4/rd_rx
|
|
TreeUpdate [SetDefaultTree]
|
|
WaveRestoreCursors {{Cursor 5} {551338181 ps} 0} {{Cursor 6} {551532200 ps} 0} {{Cursor 3} {551485343 ps} 0} {{Cursor 4} {551165292 ps} 0} {{Cursor 5} {551389395 ps} 0} {{Cursor 6} {550895270 ps} 0}
|
|
quietly wave cursor active 6
|
|
configure wave -namecolwidth 558
|
|
configure wave -valuecolwidth 56
|
|
configure wave -justifyvalue left
|
|
configure wave -signalnamewidth 0
|
|
configure wave -snapdistance 10
|
|
configure wave -datasetprefix 0
|
|
configure wave -rowmargin 4
|
|
configure wave -childrowmargin 2
|
|
configure wave -gridoffset 0
|
|
configure wave -gridperiod 1
|
|
configure wave -griddelta 40
|
|
configure wave -timeline 0
|
|
configure wave -timelineunits ns
|
|
update
|
|
WaveRestoreZoom {0 ps} {677682600 ps}
|