You've already forked gitified_old_clb_svn
177 lines
11 KiB
XML
177 lines
11 KiB
XML
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
|
<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
|
|
|
|
<!-- -->
|
|
|
|
<!-- For tool use only. Do not edit. -->
|
|
|
|
<!-- -->
|
|
|
|
<!-- ProjectNavigator created generated project file. -->
|
|
|
|
<!-- For use in tracking generated file and other information -->
|
|
|
|
<!-- allowing preservation of process status. -->
|
|
|
|
<!-- -->
|
|
|
|
<!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
|
|
|
|
<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
|
|
|
|
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="fpga.xise"/>
|
|
|
|
<files xmlns="http://www.xilinx.com/XMLSchema">
|
|
<file xil_pn:fileType="FILE_LOG" xil_pn:name="../../ip_cores/coregen.log"/>
|
|
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="_ngo"/>
|
|
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/bitgen.xmsgs"/>
|
|
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/map.xmsgs"/>
|
|
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
|
|
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/par.xmsgs"/>
|
|
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/trce.xmsgs"/>
|
|
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/xst.xmsgs"/>
|
|
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_REPORT" xil_pn:name="fpga.bgn" xil_pn:subbranch="FPGAConfiguration"/>
|
|
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BIT" xil_pn:name="fpga.bit" xil_pn:subbranch="FPGAConfiguration"/>
|
|
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGDBUILD_LOG" xil_pn:name="fpga.bld"/>
|
|
<file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="fpga.cmd_log"/>
|
|
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_DRC" xil_pn:name="fpga.drc" xil_pn:subbranch="FPGAConfiguration"/>
|
|
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="fpga.lso"/>
|
|
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="fpga.ncd" xil_pn:subbranch="Par"/>
|
|
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="fpga.ngc"/>
|
|
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGD" xil_pn:name="fpga.ngd"/>
|
|
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGR" xil_pn:name="fpga.ngr"/>
|
|
<file xil_pn:fileType="FILE_PAD_MISC" xil_pn:name="fpga.pad"/>
|
|
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAR_REPORT" xil_pn:name="fpga.par" xil_pn:subbranch="Par"/>
|
|
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PCF" xil_pn:name="fpga.pcf" xil_pn:subbranch="Map"/>
|
|
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="fpga.prj"/>
|
|
<file xil_pn:fileType="FILE_TRCE_MISC" xil_pn:name="fpga.ptwx"/>
|
|
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_STX" xil_pn:name="fpga.stx"/>
|
|
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="fpga.syr"/>
|
|
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_TXT_REPORT" xil_pn:name="fpga.twr" xil_pn:subbranch="Par"/>
|
|
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_XML_REPORT" xil_pn:name="fpga.twx" xil_pn:subbranch="Par"/>
|
|
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_UNROUTES" xil_pn:name="fpga.unroutes" xil_pn:subbranch="Par"/>
|
|
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_REPORT" xil_pn:name="fpga.ut" xil_pn:subbranch="FPGAConfiguration"/>
|
|
<file xil_pn:fileType="FILE_XPI" xil_pn:name="fpga.xpi"/>
|
|
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="fpga.xst"/>
|
|
<file xil_pn:fileType="FILE_HTML" xil_pn:name="fpga_envsettings.html"/>
|
|
<file xil_pn:fileType="FILE_NCD" xil_pn:name="fpga_guide.ncd" xil_pn:origination="imported"/>
|
|
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="fpga_map.map" xil_pn:subbranch="Map"/>
|
|
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="fpga_map.mrp" xil_pn:subbranch="Map"/>
|
|
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="fpga_map.ncd" xil_pn:subbranch="Map"/>
|
|
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGM" xil_pn:name="fpga_map.ngm" xil_pn:subbranch="Map"/>
|
|
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="fpga_map.xrpt"/>
|
|
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="fpga_ngdbuild.xrpt"/>
|
|
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_EXCEL_REPORT" xil_pn:name="fpga_pad.csv" xil_pn:subbranch="Par"/>
|
|
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_TXT_REPORT" xil_pn:name="fpga_pad.txt" xil_pn:subbranch="Par"/>
|
|
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="fpga_par.xrpt"/>
|
|
<file xil_pn:fileType="FILE_HTML" xil_pn:name="fpga_summary.html"/>
|
|
<file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="fpga_summary.xml"/>
|
|
<file xil_pn:fileType="FILE_WEBTALK" xil_pn:name="fpga_usage.xml"/>
|
|
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="fpga_xst.xrpt"/>
|
|
<file xil_pn:fileType="FILE_HTML" xil_pn:name="usage_statistics_webtalk.html"/>
|
|
<file xil_pn:fileType="FILE_LOG" xil_pn:name="webtalk.log"/>
|
|
<file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="webtalk_pn.xml"/>
|
|
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xlnx_auto_0_xdb"/>
|
|
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xst"/>
|
|
</files>
|
|
|
|
<transforms xmlns="http://www.xilinx.com/XMLSchema">
|
|
<transform xil_pn:end_ts="1373990517" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1373990516">
|
|
<status xil_pn:value="SuccessfullyRun"/>
|
|
<status xil_pn:value="ReadyToRun"/>
|
|
</transform>
|
|
<transform xil_pn:end_ts="1374246861" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="8328376395042630697" xil_pn:start_ts="1374246861">
|
|
<status xil_pn:value="SuccessfullyRun"/>
|
|
<status xil_pn:value="ReadyToRun"/>
|
|
</transform>
|
|
<transform xil_pn:end_ts="1374247066" xil_pn:in_ck="9040185842282866933" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-1007043285765790770" xil_pn:start_ts="1374247066">
|
|
<status xil_pn:value="SuccessfullyRun"/>
|
|
<status xil_pn:value="ReadyToRun"/>
|
|
<outfile xil_pn:name="../../ip_cores/fifo.ngc"/>
|
|
<outfile xil_pn:name="../../ip_cores/fifo.vhd"/>
|
|
<outfile xil_pn:name="../../ip_cores/fifo_synth.vhd"/>
|
|
</transform>
|
|
<transform xil_pn:end_ts="1373990517" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1373990517">
|
|
<status xil_pn:value="SuccessfullyRun"/>
|
|
<status xil_pn:value="ReadyToRun"/>
|
|
</transform>
|
|
<transform xil_pn:end_ts="1374246861" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-5857749120703762379" xil_pn:start_ts="1374246861">
|
|
<status xil_pn:value="SuccessfullyRun"/>
|
|
<status xil_pn:value="ReadyToRun"/>
|
|
</transform>
|
|
<transform xil_pn:end_ts="1373990517" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="-5918749233538361311" xil_pn:start_ts="1373990517">
|
|
<status xil_pn:value="SuccessfullyRun"/>
|
|
<status xil_pn:value="ReadyToRun"/>
|
|
</transform>
|
|
<transform xil_pn:end_ts="1374246861" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="7778922290640757272" xil_pn:start_ts="1374246861">
|
|
<status xil_pn:value="SuccessfullyRun"/>
|
|
<status xil_pn:value="ReadyToRun"/>
|
|
</transform>
|
|
<transform xil_pn:end_ts="1375115496" xil_pn:in_ck="4446858449523094432" xil_pn:name="TRANEXT_xstsynthesize_virtex6" xil_pn:prop_ck="-2463610088276617568" xil_pn:start_ts="1375115415">
|
|
<status xil_pn:value="AbortedRun"/>
|
|
<status xil_pn:value="WarningsGenerated"/>
|
|
<status xil_pn:value="ReadyToRun"/>
|
|
<status xil_pn:value="OutOfDateForInputs"/>
|
|
<status xil_pn:value="OutOfDateForOutputs"/>
|
|
<status xil_pn:value="InputAdded"/>
|
|
<status xil_pn:value="InputChanged"/>
|
|
<status xil_pn:value="InputRemoved"/>
|
|
<status xil_pn:value="OutputRemoved"/>
|
|
</transform>
|
|
<transform xil_pn:end_ts="1374253677" xil_pn:in_ck="-2190586819162554236" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="671693622354353866" xil_pn:start_ts="1374253677">
|
|
<status xil_pn:value="SuccessfullyRun"/>
|
|
<status xil_pn:value="ReadyToRun"/>
|
|
</transform>
|
|
<transform xil_pn:end_ts="1374253707" xil_pn:in_ck="-1494076234943613205" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="6129204007290791508" xil_pn:start_ts="1374253677">
|
|
<status xil_pn:value="SuccessfullyRun"/>
|
|
<status xil_pn:value="ReadyToRun"/>
|
|
<status xil_pn:value="OutOfDateForInputs"/>
|
|
<status xil_pn:value="OutOfDateForPredecessor"/>
|
|
<status xil_pn:value="OutOfDateForOutputs"/>
|
|
<status xil_pn:value="InputAdded"/>
|
|
<status xil_pn:value="InputRemoved"/>
|
|
<status xil_pn:value="OutputRemoved"/>
|
|
</transform>
|
|
<transform xil_pn:end_ts="1374254043" xil_pn:in_ck="308435453584025417" xil_pn:name="TRANEXT_map_virtex7" xil_pn:prop_ck="1066978947743128725" xil_pn:start_ts="1374253707">
|
|
<status xil_pn:value="SuccessfullyRun"/>
|
|
<status xil_pn:value="WarningsGenerated"/>
|
|
<status xil_pn:value="ReadyToRun"/>
|
|
<status xil_pn:value="OutOfDateForInputs"/>
|
|
<status xil_pn:value="OutOfDateForPredecessor"/>
|
|
<status xil_pn:value="OutOfDateForOutputs"/>
|
|
<status xil_pn:value="InputRemoved"/>
|
|
<status xil_pn:value="OutputRemoved"/>
|
|
</transform>
|
|
<transform xil_pn:end_ts="1374254218" xil_pn:in_ck="-406685678899006750" xil_pn:name="TRANEXT_par_virtex5" xil_pn:prop_ck="3510646383847945537" xil_pn:start_ts="1374254043">
|
|
<status xil_pn:value="SuccessfullyRun"/>
|
|
<status xil_pn:value="WarningsGenerated"/>
|
|
<status xil_pn:value="ReadyToRun"/>
|
|
<status xil_pn:value="OutOfDateForInputs"/>
|
|
<status xil_pn:value="OutOfDateForPredecessor"/>
|
|
<status xil_pn:value="OutOfDateForOutputs"/>
|
|
<status xil_pn:value="InputRemoved"/>
|
|
<status xil_pn:value="OutputRemoved"/>
|
|
</transform>
|
|
<transform xil_pn:end_ts="1374254353" xil_pn:in_ck="4495873352257" xil_pn:name="TRANEXT_bitFile_virtex7" xil_pn:prop_ck="3160107541638749219" xil_pn:start_ts="1374254218">
|
|
<status xil_pn:value="SuccessfullyRun"/>
|
|
<status xil_pn:value="WarningsGenerated"/>
|
|
<status xil_pn:value="ReadyToRun"/>
|
|
<status xil_pn:value="OutOfDateForInputs"/>
|
|
<status xil_pn:value="OutOfDateForPredecessor"/>
|
|
<status xil_pn:value="OutOfDateForOutputs"/>
|
|
<status xil_pn:value="InputRemoved"/>
|
|
<status xil_pn:value="OutputRemoved"/>
|
|
</transform>
|
|
<transform xil_pn:end_ts="1374254218" xil_pn:in_ck="308435453584025285" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416184" xil_pn:start_ts="1374254174">
|
|
<status xil_pn:value="SuccessfullyRun"/>
|
|
<status xil_pn:value="ReadyToRun"/>
|
|
<status xil_pn:value="OutOfDateForInputs"/>
|
|
<status xil_pn:value="OutOfDateForPredecessor"/>
|
|
<status xil_pn:value="OutOfDateForOutputs"/>
|
|
<status xil_pn:value="InputRemoved"/>
|
|
<status xil_pn:value="OutputRemoved"/>
|
|
</transform>
|
|
</transforms>
|
|
|
|
</generated_project>
|